
BR93LC46-W / BR93LC46F-W / BR93LC46RF-W /
Memory ICs
BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W
(7) All address write (Fig.13)
   With this command, the input 16 bits data is written simultaneously to all of the addresses (64 words). Rather than
   writing one word at a time, in succession, data is written all at one time, enabling a write time of t
E / W
.
CS
SK
DI
DO
High  Z
0
0
1
0
1
D15
D14
D1
D0
1
2
5
10
25
STATUS
t
SV
READY
BUSY
t
CS
t
E / W
Fig.13  Write all address cycle timing. (WRAL)
(8) Write disable (Fig.14)
   When the power supply is turned on, the IC enters the write disable status. Similarly, when the write disable command
   is issued, the IC enters the same status. When in this status, all write commands are ignored, but read commands
   may be executed.
   In the write enable status, writing begins even if a write command is entered accidentally. To prevent errors of this type,
   we recommend executing a write disable command after writing has been completed.
1
0
0
0
0
CS
SK
DI
DO
High  Z
Fig.14  Write disable cycle timing (WDS)
z
Operation notes
(1) Cancelling modes
Fig.15
a
b
t
E / W
WRITE, WRAL
READ
1 bit
2 bits
6 bits
16 bits
Start bit
Operating code
Address
Data
1 bit
2 bits
6 bits
16 bits
Start bit
Operating code
Address
Data
Cancel can be performed for the entire read mode space
Cancellation method: CS LOW
a: Canceled by setting CS LOW or V
CC 
OFF (
)
b: Cannot be canceled by any method. If V
CC
 is set to OFF during this time, the data in the
    designated address is not secured.
 V
CC
 OFF (V
CC
 is turned off after CS is set to LOW)