參數(shù)資料
型號(hào)： BQ4285EP
廠商： Texas Instruments
文件頁(yè)數(shù)： 31/31頁(yè)
文件大小： 0K
描述： IC RTC W/114X8 NVSRAM 24-DIP
產(chǎn)品培訓(xùn)模塊： Clock Basics in 10 minutes or less
標(biāo)準(zhǔn)包裝： 15
類型： 時(shí)鐘/日歷
特點(diǎn)： 警報(bào)器，夏令時(shí)，閏年，NVSRAM，方波輸出
存儲(chǔ)容量： 114B
時(shí)間格式： HH:MM:SS（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： 并聯(lián)
電源電壓： 4.5 V ~ 5.5 V
電壓 - 電源，電池： 2.5 V ~ 4 V
工作溫度： 0°C ~ 70°C
安裝類型： 通孔
封裝/外殼： 24-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 24-PDIP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 1076 (CN2011-ZH PDF)
其它名稱： 296-6525-5
Control/Status Registers
The four control/status registers of the bq4285E/L are
accessible regardless of the status of the update cycle
(see Table 4).
Register A
Register A programs:
n
The frequency of the square-wave and the periodic
event rate.
n
Oscillator operation.
Register A provides:
n
Status of the update cycle.
RS0–RS3 - Frequency Select
These bits select one of the 13 frequencies for the SQW out-
put and the periodic interrupt rate, as shown in Table 3.
OS0–OS2 - Oscillator Control
These three bits control the state of the oscillator and di-
vider stages. A pattern of 010 enables RTC operation by
turning on the oscillator and enabling the frequency di-
vider. A pattern of 011 behaves as 010 but additionally
transforms register C into a read/write register. This al-
lows the 32.768kHz output on the square wave pin to be
turned on. A pattern of 11X turns the oscillator on, but
keeps the frequency divider disabled. When 010 is writ-
ten, the RTC begins its first update after 500ms.
UIP - Update Cycle Status
This read-only bit is set prior to the update cycle. When
UIP equals 1, an RTC update cycle may be in progress.
UIP is cleared at the end of each update cycle. This bit
is also cleared when the update transfer inhibit (UTI)
bit in register B is 1.
Register B
Register B enables:
n
Update cycle transfer operation
n
Square-wave output
n
Interrupt events
n
Daylight saving adjustment
Register B selects:
n
Clock and calendar data formats
All bits of register B are read/write.
9
bq4285E/L
76543210
----
RS3
RS2
RS1
RS0
76543210
-
OS2
OS1
OS0
----
Register A Bits
76543210
UIP
OS2
OS1
OS0
RS3
RS2
RS1
RS0
76543210
UIP
-------
Register B Bits
7654
3
210
UTI
PIE
AIE
UIE SQWE
DF
HF
DSE
Reg.
Loc.
(Hex) Read Write
Bit Name and State on Reset
7 (MSB)
6
5
4
3
2
1
0 (LSB)
A
0A
Yes
1
UIP
na
OS2
na
OS1
na
OS0 na
RS3
na
RS2
na
RS1
na
RS0
na
B
0B
Yes
UTI
na
PIE
0
AIE
0
UIE
0
SQWE
0
DF
na
HF
na
DSE na
C
0C
Yes
No
2
INTF
0
PF
0
AF
0
UF
0
-
0
32KE na
-
0
-
0
D
0D
Yes
No
VRT
na
-0-0-
0
-
0-0-0
-
0
Notes:
na = not affected.
1.
Except bit 7.
2.
Read/write only when OSC2–OSC0 in register A is 011 (binary).
Table 4. Control/Status Registers
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