參數(shù)資料
型號: BQ4285EP
廠商: Texas Instruments
文件頁數(shù): 12/31頁
文件大小: 0K
描述: IC RTC W/114X8 NVSRAM 24-DIP
產(chǎn)品培訓(xùn)模塊: Clock Basics in 10 minutes or less
標(biāo)準(zhǔn)包裝: 15
類型: 時鐘/日歷
特點: 警報器,夏令時,閏年,NVSRAM,方波輸出
存儲容量: 114B
時間格式: HH:MM:SS(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: 并聯(lián)
電源電壓: 4.5 V ~ 5.5 V
電壓 - 電源,電池: 2.5 V ~ 4 V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 24-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 24-PDIP
包裝: 管件
產(chǎn)品目錄頁面: 1076 (CN2011-ZH PDF)
其它名稱: 296-6525-5
Block Diagram
standard CMOS SRAM nonvolatile during power-fail
conditions. During power-fail, the bq4285E/L auto-
matically write-protects the external SRAM and pro-
vides a VCC output sourced from the clock backup
battery.
Pin Descriptions
AD0–AD7
Multiplexed address/data input/
output
The bq4285E/L bus cycle consists of two
phases: the address phase and the data-
transfer phase. The address phase precedes
the data-transfer phase.
During the ad-
dress phase, an address placed on AD0–AD7
is latched into the bq4285E/L on the falling
edge of the AS signal.
During the data-
transfer phase of the bus cycle, the AD0–AD7
pins serve as a bidirectional data bus.
MOT
Connect to VSS for normal operation
The setting should not be changed during
system operation. MOT is internally pulled
low by a 20K
resistor. For the DIP and
SOIC packages, this pin is internally con-
nected to VSS, enabling the bus timing for
the Intel architecture.
CS
Chip select input
CS should be driven low and held stable
during the data-transfer phase of a bus cy-
cle accessing the bq4285E/L.
2
Bus
Type
MOT
Level
DS
Equivalent
R/W
Equivalent
AS
Equivalent
Intel
VSS
RD,
MEMR, or
I/OR
WR,
MEMW, or
I/OW
ALE
Table 1. Bus Setup
bq4285E/L
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