
PEC Calculation
The basis of the PEC calculation is an 8-bit Cyclic Re-
dundancy Check (CRC-8) based on the polynomial C(X)
= X
8
+ X
2
+ X
1
+ 1. The PEC calculation includes all
bytes in the transmission, including address, command,
and data.
The PEC calculation does not include AC-
KNOWLEDGE, NOT ACKNOWLEDGE, START, STOP,
and Repeated START bits.
For example, the host requests RemainingCapacity()
from the bq2060. This includes the host following the
Read Word protocol.
The bq2060 calculates the PEC
based on the following 5 bytes of data, assuming the re-
maining capacity of thebattery is 1001mAh.
Battery Address with R/W = 0: 0x16
Command Codefor RemainingCapacity(): 0x0f
Battery Address with R/W = 1: 0x17
RemainingCapacity(): 0x03e9
For 0x160f17e903, the bq2060 transmits a PEC of 0xe8
tothehost.
PEC Enable in Master Mode
PEC for master mode broadcasts to the charger, host, or
both can be enabled/disabled with the combination of
thebits HPE and CPE in
 Control Mode.
SMBus On and Off State
The bq2060 detects whether the SMBus enters the Off
State” by monitoring the SMBC and SMBD lines. When
both signals are continually low for at least 2.5s, the
bq2060 detects the Off State. When the SMBC and
SMBD lines go high, the bq2060 detects the On State
and can begin communication within 1ms. One-M
pulldown resistors on SMBC and SMBD
mended for reliable
OH State
detection.
are recom-
HDQ16
The HDQ16 interface is a command-based protocol. (See
Figure 6.) A processor sends the command code to the
bq2060. The 8-bit command code consists of two fields,
the 7-bit HDQ16 command code (bits 0–6) and the 1-bit
R/W field (MSB bit 7). The R/W field directs the bq2060
either to
Storethenext 16 bits of data toa specified register or
Output 16 bits of data from thespecified register
With HDQ16, the least significant bit (LSB) of a data
byte(command) or word (data) is transmitted first.
A bit transmission consists of three distinct sections. The
first section starts the transmission by either the host or
the bq2060 taking the HDQ16 pin to a logic-low state for
a period t
S T R H ;B
. T he next section is the actual
data-transmission, where the data bit is valid by the
time, t
DSU;B
 after the negative edge used to start commu-
nication. The data bit is held for a period t
DH;DV
 to allow
thehost processor or bq2060 tosamplethedata bit.
The final section is used to stop the transmission by re-
turning the HDQ16 pin to a logic-high state by at least
the time t
SSU;B
 after the negative edge used to start
communication. The final logic-high state should be un-
til a period t
CYCH;B
 to allow time to ensure that the bit
transmission was stopped properly.
If a communication error occurs (e.g., t
CYCB
 > 250
μ
s),
the host sends the bq2060 a BREAK to reinitiate the se-
rial interface. The bq2060 detects a BREAK when the
HDQ16 pin is in a logic-low state for a time t
B
 or
greater. The HDQ16 pin is then returned to its normal
15
Send Host to bq2060
HDQ Command Code
Send Host to bq2060 or
Receive from bq2060
16 bit Data
Break
LSB
Bit0
R/W
MSB
Bit7
TD2060CE.eps
Start-bit
Address-Bit/
Data-Bit
Stop-Bit
tRR
tRSPS
Figure 6. HDQ16 Communication Example
bq2060