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參數(shù)資料
| 型號： | B300W35A102XYG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 10/15頁 |
| 文件大小： | 0K |
| 描述： | IC PROCESSOR AUDIO 24BIT 35WLCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | BelaSigna® 300 |
| 類型： | 音頻處理器 |
| 應(yīng)用： | 便攜式設(shè)備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 35-VFBGA，WLCSP |
| 供應(yīng)商設(shè)備封裝： | 35-WLCSP（3.63x2.68） |
| 包裝： | 帶卷 (TR) |
BelaSigna 300
http://onsemi.com
4
Table 2. ELECTRICAL SPECIFICATIONS (continued)
Description
Screened
Units
Max
Typ
Min
Conditions
Symbol
VDBL (1 mF External Capacitor)
Regulator PSRR
VDBLPSRR
1 kHz
35
41
dB
Load current
ILOAD
2.5
mA
Load regulation
LOADREG
7
10
mV/mA
√
Line regulation
LINEREG
10
20
mV/V
VDDC (1 mF External Capacitor)
Digital supply voltage output
VDDC
Configured by a control register
0.79
0.95
1.25
V
√
VDDC output level adjustment
VDDCSTEP
27
29
31
mV
Regulator PSRR
VDDCPSRR
1 kHz
25
25.5
26
dB
Load current
ILOAD
3.5
mA
Load regulation
LOADREG
3
12
mV/mA
√
Line regulation
LINEREG
3
8
mV/V
POWERONRESET (POR)
POR startup voltage
VDDCSTARTUP
0.775
0.803
0.837
V
POR shutdown voltage
VDDCSHUTDOWN
0.755
0.784
0.821
V
POR hysteresis
PORHYSTERESIS
13.8
19.1
22.0
mV
POR duration
TPOR
11.0
11.6
12.3
ms
INPUT STAGE
Analog input voltage
VIN
0
2
V
Preamplifier gain tolerance
PAG
1 kHz
1
0
1
dB
√
Input impedance
RIN
0 dB preamplifer gain
239
kW
Nonzero preamplifier gains
550
578
615
kW
√
Input referred noise
INIRN
Unweighted,
100 Hz to 10 kHz BW
Preamplifier setting:
0 dB
12 dB
15 dB
18 dB
21 dB
24 dB
27 dB
30 dB (Note 4)
39
10
7
6
4.5
4
3.5
3
50
12
9
8
5.5
5
4.5
4
mVrms
√
Input dynamic range
INDR
1 kHz, 20 Hz to 8 kHz BW
Preamplifier setting:
0 dB
12 dB
15 dB
18 dB
21 dB
24 dB
27 dB
30 dB
85
84
83
82
81
80
78
89
88
87
86
85
83
81
dB
Input peak THD+N
INTHDN
Any valid preamplifier gain, 1 kHz
70
63
dB
√
4. DFN Package option can have higher inputreferred noise up to 2 mV worse than the WLCSP. WLCSP specifications listed.
5. CDM only applies to the DFN package.
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