參數(shù)資料
型號： 0W344-005-XTP
廠商： ON Semiconductor
文件頁數(shù)： 1/43頁
文件大?。?/td> 0K
描述： DSP BELASIGNA 200 AUDIO 52-NQFN
產(chǎn)品變化通告： BelaSigna 200 QFN Obsolescence 09/Dec/2009
標準包裝： 1,000
系列： BelaSigna® 200
類型： 音頻處理器
應(yīng)用： 便攜式設(shè)備
安裝類型： 表面貼裝
封裝/外殼： 52-TFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 52-NQFP（8x8）
包裝： 帶卷 (TR)
2008 SCILLC. All rights reserved.
Publication Order Number:
June 2008 – Rev. 16
BELASIGNA200/D
BelaSigna 200
1.0 General Description
BelaSigna 200 is a high-performance, programmable, mixed-signal digital signal processor (DSP) that is based on
ON Semiconductor’s patented second-generation SignaKlara technology.
This single-chip solution is ideally suited for embedded applications where audio performance, low power consumption and
miniaturization are critical. BelaSigna 200 targets a wide variety of digital speech- and audio-centric applications, including:
Communication headsets
Smart phones
Personal digital assistants (PDAs)
Hands-free car kits
Bluetooth wireless technology systems
BelaSigna 200 provides numerous analog and digital interfaces including parallel, serial, synchronous, and asynchronous interfaces to
facilitate the connection with transducers from various applications.
BelaSigna 200 contains two primary processing blocks, which all work together to provide a complete audio processing chain. The
analog section includes two 16-bit A/D converters and two 16-bit D/A converters. Two on-chip direct digital output stages allow
BelaSigna 200 to drive various output transducers directly, eliminating the need for external power amplifiers.
BelaSigna 200 features internal clock generation and power regulation for excellent noise and power performance. Two DSP
subsystems operate concurrently: the RCore, which is a fully programmable DSP core, and the weighted overlap-add (WOLA)
filterbank coprocessor, which is a dedicated, configurable processor that executes time-frequency domain transforms and other vector-
based computations. In addition to these processors, there are several other peripherals, which optimize the architecture to audio
processing, such as the onput/output processor (IOP) – an audio-targeted direct memory access (DMA) processor, which runs in the
background and manages the data flow between the converters and the two processors. The BelaSigna 200 functional block diagram is
shown in Figure 1.
Figure 1: BelaSigna 200 Functional Block Diagram
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參數(shù)描述
0W588-002-XUA 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC BELASIGNA 200 WLCSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
0W589-005-XDS 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC AUDIO AD/DA RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風格: 封裝 / 箱體: 封裝:
0W589-007-XDS 功能描述:音頻模/數(shù)轉(zhuǎn)換器 IC AUDIO AD/DA RoHS:否 制造商:Wolfson Microelectronics 轉(zhuǎn)換速率: 分辨率: ADC 輸入端數(shù)量: 工作電源電壓: 最大工作溫度: 最小工作溫度: 安裝風格: 封裝 / 箱體: 封裝:
0W598001EVK 制造商:ON Semiconductor 功能描述:B250 EDK SGL PURCH - Bulk
0W633-001-XTP 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC BELASIGNA 250 CABGA 5X5 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
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