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參數(shù)資料
| 型號： | B250W48A106XXG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 8/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR AUDIO 16BIT 48WLCSP |
| 標準包裝： | 2,500 |
| 系列： | BelaSigna® 250 |
| 類型： | 音頻處理器 |
| 應用： | 便攜式設備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFBGA，WLCSP |
| 供應商設備封裝： | 48-WLCSP（3.8x2.58） |
| 包裝： | 帶卷 (TR) |
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BELASIGNA 250
http://onsemi.com
16
Instruction
Description
MSET Reg, (Ri) [,SQ]
Multiplier load
MUL [Cond] [,A] [,P]
Update A and/or PH | PL with X*Y on
condition
NEG A [,Cond] [,DW]
Calculate negative value of A
on condition
NOP
No operation
OR A, Reg
OR register with AH to AH
OR A, (Rij)
OR memory with AH to AH
OR A, DRAM [,B]
OR (DRAM) with AH to AH
OR A, (Rij)p
OR program memory with AH to AH
OR A, Rc
OR Rc register with AH to AH
ORI A, IMM
OR IMM with AH to AH
ORSI A, SIMM
OR unsigned SIMM with AH to AH
POP Reg [,B]
Pop register from stack
POP Rc [,B]
Pop Rc register from stack
PUSH Reg [,B]
Push register on stack
PUSH Rc [,B]
Push Rc register on stack
PUSH IMM [,B]
Push IMM on stack
REP n
Repeat next instruction n+1 times
(9bit unsigned)
REP Reg
Repeat next instruction Reg+1 times
REP (Rij)
Repeat next instruction (Rij)+1 times
RES Reg, Bit
Clear bit in register
RES (Rij), Bit
Clear bit in memory
RET [B]
Return from subroutine
RND A
Round A with AL
SET Reg, Bit
Set bit in register
SET (Rij), Bit
Set bit in memory
SET_IE
Set interrupt enable flag
SHFT n
Shift A by ± n bits (6bit signed)
SHFT A [,Cond] [,INV]
Shift A by EXP bits on condition
SLEEP [IE]
Sleep
Instruction
Description
SUB A, Reg [,C]
Subtract register from A
SUB A, (Rij) [,C]
Subtract memory from A
SUB A, DRAM [,B]
Subtract (DRAM) from A
SUB A, (Rij)p [,C]
Subtract program memory from A
SUB A, Rc [,C]
Subtract Rc register from A
SUBI A, IMM [,C]
Subtract IMM from A
SUSI A, SIMM
Subtract signed SIMM from A
SWAP A [,Cond]
Swap AH, AL on condition
TGL Reg, Bit
Toggle bit in register
TGL (Rij), Bit
Toggle bit in memory
TST Reg, Bit
Test bit in register
TST (Rij), Bit
Test bit in memory
Table 8. NOTATION
Symbol
Meaning
A
Accumulator update
B
Memory bank selection (X or Y)
C
Carry bit
Cond
Condition in status register
DRAM
Low data (X or Y) memory address (8bits)
DW
Double word
IE
Interrupt enable flag
IMM
Immediate data (16bits)
INV
Inverse shift
P
PH | PL update
PRAM
Program memory address (16bits)
Rc
Rc register (R0..7, PCFG0..2, PCFG4..6, LC0/1)
Reg
Data register (AL, AH, X, Y, ST, PC, PL, PH,
EXT0, EXP, AE, EXT3..EXT7)
Ri / Rj / Rij
Pointer to X / Y / either data memory
SIMM
Short immediate data (10bits)
SQ
Square
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