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參數(shù)資料
| 型號： | B250W48A106XXG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 7/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR AUDIO 16BIT 48WLCSP |
| 標準包裝： | 2,500 |
| 系列： | BelaSigna® 250 |
| 類型： | 音頻處理器 |
| 應用： | 便攜式設備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFBGA，WLCSP |
| 供應商設備封裝： | 48-WLCSP（3.8x2.58） |
| 包裝： | 帶卷 (TR) |
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BELASIGNA 250
http://onsemi.com
15
Table 7. INSTRUCTION SET
Instruction
Description
ABS A [,Cond] [,DW]
Calculate absolute value of A
on condition
ADD A, Reg [,C]
Add register to A
ADD A, (Rij) [,C]
Add memory to A
ADD A, DRAM [,B]
Add (DRAM) to A
ADD A, (Rij)p [,C]
Add program memory to A
ADD A, Rc [,C]
Add Rc register to A
ADDI A, IMM [,C]
Add IMM to A
ADSI A, SIMM
Add signed SIMM to A
AND A, Reg
AND register with AH to AH
AND A, (Rij)
AND memory with AH to AH
AND A, DRAM [,B]
AND (DRAM) with AH to AH
AND A, (Rij)p
AND program memory with AH to AH
AND A, Rc
AND Rc register with AH to AH
ANDI A, IMM
AND IMM with AH to AH
ANSI A, SIMM
AND unsigned SIMM with AH to AH
BRA PRAM [,Cond]
Branch to new address on condition
BREAK
Stop the DSP for debugging purposes
CALL PRAM [,Cond] [,B] Push PC and branch to new address
on condition
CLB A
Calculate the leading bits on A
CLR A [,DW]
Clear accumulator
CLR Reg
Clear register
CMP A, Reg [,C]
Compare register to A
CMP A, (Rij) [,C]
Compare memory to A
CMP A, DRAM [,B]
Compare (DRAM) to A
CMP A, (Rij)p [,C]
Compare program memory to A
CMP A, Rc [,C]
Compare Rc register to A
CMPI A, IMM [,C]
Compare IMM to A
CMSI A, SIMM
Compare signed SIMM to A
CMPL A [,Cond] [,DW]
Calculate logical inverse of A
on condition
DADD [Cond] [,P]
Add PH | PL to A, update PH | PL on
condition
DBNZ0/1 PRAM
Branch to new address if LC0/1 <> 0
DCMP
Compare PH | PL to A
DEC A [,Cond] [,DW]
Decrement A on condition
DEC Reg [Cond]
Decrement register on condition
DEC (Rij) [,Cond]
Decrement memory on condition
DSUB [Cond] [,P]
Subtract PH | PL from A, update
PH | PL on condition
EOR A, Reg
ExclusiveOR register with AH to AH
EOR A, (Rij)
ExclusiveOR memory with AH to AH
Instruction
Description
EOR A, DRAM [,B]
ExclusiveOR (DRAM) with AH to AH
EOR A, (Rij)p
ExclusiveOR program memory with
AH to AH
EOR A, Rc
ExclusiveOR Rc register with
AH to AH
EORI A, IMM
ExclusiveOR IMM with AH to AH
EOSI A, SIMM
ExclusiveOR unsigned SIMM with
AH to AH
INC A [,Cond] [,DW]
Increment A on condition
INC Reg [,Cond]
Increment register on condition
INC (Rij) [,Cond]
Increment memory on condition
LD Rc, Rc
Load Rc register with Rc register
LD Reg, Reg
Load register with register
LD Reg, (Rij)
Load register with memory
LD (Rij), Reg
Load memory with register
LD (Ri), (Rj)
Transfer Y mem data to X mem
LD (Rj), (Ri)
Transfer X mem data to Y mem
LD A, DRAM [,B]
Load A with (DRAM)
LD DRAM, A [,B]
Load (DRAM) with A
LD Rc, (Rij)
Load Rc register with memory
LD (Rij), Rc
Load memory with Rc register
LD Reg, (Rij)p
Load register with program memory
LD (Rij)p, Reg
Load program memory with register
LD Reg, (Reg)p
Load register with program memory
via register
LD Reg, Rc
Load register with Rc register
LD Rc, Reg
Load Rc register with register
LDI Reg, IMM
Load register with IMM
LDI Rc, IMM
Load Rc register with IMM
LDI (Rij), IMM
Load memory with IMM
LDSI LC0/1 SIMM
Load loop counter with 16bit unsigned
SIMM
LDSI A, SIMM
Load A with signed SIMM
LDSI Rij, SIMM
Load pointer register with unsigned
SIMM
MLD (Rj), (Ri) [,SQ]
Multiplier load and clear A
MLD Reg, (Ri) [,SQ]
Multiplier load and clear A
MODR Rj, Ri
Pointer register modification
MPYA (Rj), (Ri) [,SQ]
Multiplier load and accumulate
MPYA Reg, (Ri) [,SQ]
Multiplier load and accumulate
MPYS (Rj), (Ri) [,SQ]
Multiplier load and accumulate
negative
MPYS Reg, (Ri) [,SQ]
Multiplier load and accumulate
negative
MSET (Rj), (Ri) [,SQ]
Multiplier load
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