
ASIX ELECTRONICS CORPORATION
35
AX88796 L 3-in-1 Local Bus Fast Ethernet Controller
5.1.3 Interrupt mask register (IMR) Offset 0FH (Write)
FIELD
NAME
7
-
Reserved
6
RDCE DMA Complete Interrupt Enable. Default “l(fā)ow” disabled.
5
CNTE Counter Overflow Interrupt Enable. Default “l(fā)ow” disabled.
4
OVWE Overwrite Interrupt Enable. Default “l(fā)ow” disabled.
3
TXEE Transmit Error Interrupt Enable. Default “l(fā)ow” disabled.
2
RXEE Receive Error Interrupt Enable. Default “l(fā)ow” disabled.
1
PTXE Packet Transmitted Interrupt Enable. Default “l(fā)ow” disabled.
0
PRXE Packet Received Interrupt Enable. Default “l(fā)ow” disabled.
DESCRIPTION
5.1.4 Data Configuration Register (DCR) Offset 0EH (Write)
FIELD
NAME
7
RDCR Remote DMA always completed
6:2
-
Reserved
1
-
Reserved
0
WTS
Word Transfer Select
0 : Selects byte-wide DMA transfers.
1 : Selects word-wide DMA transfers.
DESCRIPTION
5.1.5 Transmit Configuration Register (TCR) Offset 0DH (Write)
FIELD
NAME
7
FDU
Full Duplex :
This bit indicates the current media mode is Full Duplex or not.
0 : Half duplex
1 : Full duplex
6
PD
Pad Disable
0 : Pad will be added when packet length less than 60.
1 : Pad will not be added when packet length less than 60.
5
RLO
Retry of late collision
0 : Don’t retransmit packet when late collision happens.
1 : Retransmit packet when late collision happens.
4:3
-
Reserved
2:1
LB1,LB0 Encoded Loop-back Control
These encoded configuration bits set the type of loop-back that is to be performed.
LB1 LB0
Mode 0 0 0 Normal operation
Mode 1 0 1 Internal AX88796 loop-back
Mode 2 1 0 PHYcevisor loop-back
0
CRC
Inhibit CRC
0 : CRC appended by transmitter.
1 : CRC inhibited by transmitter.
DESCRIPTION