
ASIX ELECTRONICS CORPORATION
33
AX88796 L 3-in-1 Local Bus Fast Ethernet Controller
PAGE 1 (PS1=0,PS0=1)
OFFSET
00H
READ
WRITE
Command Register
( CR )
Physical Address Register 0
( PARA0 )
Physical Address Register 1
( PARA1 )
Physical Address Register 2
( PARA2 )
Physical Address Register 3
( PARA3 )
Physical Address Register 4
( PARA4 )
Physical Address Register 5
( PARA5 )
Current Page Register
( CPR )
Multicast Address Register 0
( MAR0 )
Multicast Address Register 1
( MAR1 )
Multicast Address Register 2
( MAR2 )
Multicast Address Register 3
( MAR3 )
Multicast Address Register 4
( MAR4 )
Multicast Address Register 5
( MAR5 )
Multicast Address Register 6
( MAR6 )
Multicast Address Register 7
( MAR7 )
Data Port
Inter-frame Gap Segment 1
IFGS1
Inter-frame Gap Segment 2
IFGS2
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
GPI
Standard Printer Port (SPP)
Reserved
Reset
Command Register
( CR )
Physical Address Register 0
( PAR0 )
Physical Address Register 1
( PAR1 )
Physical Address Register 2
( PAR2 )
Physical Address Register 3
( PAR3 )
Physical Address Register 4
( PAR4 )
Physical Address Register 5
( PAR5 )
Current Page Register
( CPR )
Multicast Address Register 0
( MAR0 )
Multicast Address Register 1
( MAR1 )
Multicast Address Register 2
( MAR2 )
Multicast Address Register 3
( MAR3 )
Multicast Address Register 4
( MAR4 )
Multicast Address Register 5
( MAR5 )
Multicast Address Register 6
( MAR6 )
Multicast Address Register 7
( MAR7 )
Data Port
Inter-frame Gap Segment 1
IFGS1
Inter-frame Gap Segment 2
IFGS2
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
GPOC
Standard Printer Port (SPP)
Reserved
Reserved
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H, 11H
12H
13H
14H
15H
16H
17H
18H - 1AH
1BH - 1EH
1FH
Tab - 13 Page 1 of MAC Core Registers Mapping