參數(shù)資料
型號： AX88796L
廠商： Electronic Theatre Controls, Inc.
英文描述： 3-in-1 Local Bus Fast Ethernet Controller
中文描述： 3合1本地總線快速以太網(wǎng)控制器
文件頁數(shù)： 3/71頁
文件大?。?/td> 931K
代理商： AX88796L
ASIX ELECTRONICS CORPORATION
3
AX88796 L 3-in-1 Local Bus Fast Ethernet Controller
5.1.13 Test Register (TR) Offset 15H (Write).................................................................................................... 37
5.1.14 Test Register (TR) Offset 15H (Read) .................................................................................................... 38
5.1.15 General Purpose Input Register (GPI) Offset 17H (Read)...................................................................... 38
5.1.16 GPO and Control (GPOC) Offset 17H (Write)....................................................................................... 38
5.1.17 SPP Data Port Register (SPP_DPR) Offset 18H (Read/Write)............................................................... 39
5.1.18 SPP Status Port Register (SPP_SPR) Offset 19H (Read)........................................................................ 39
5.1.19 SPP Command Port Register (SPP_CPR) Offset 1AH (Read/Write)....................................................... 39
5.2 T
HE
E
MBEDDED
PHY R
EGISTERS
..................................................................................................................... 40
5.2.1 MR0 -- Control Register Bit Descriptions................................................................................................. 41
5.2.2 MR1 -- Status Register Bit Descriptions................................................................................................... 42
5.2.3 MR2, MR3 -- Identification Registers (1 and 2) Bit Descriptions.............................................................. 43
5.2.4 MR4 – Autonegotiation Advertisement Registers Bit Descriptions............................................................ 43
5.2.5 MR5 – Autonegotiation Link Partner Ability (Base Page) Register Bit Descriptions................................. 43
5.2.6 MR5 –Autonegotiation Link Partner(LP)Ability Register (Next Page)Bit Descriptions............................. 44
5.2.7 MR6 – Autonegotiation Expansion Register Bit Descriptions................................................................... 44
5.2.8 MR7 –Next Page Transmit Register Bit Descriptions ............................................................................... 45
5.2.9 MR16 – PCS Control Register Bit Descriptions........................................................................................ 45
5.2.10 MR17 –Autonegotiation Register A Bit Descriptions.............................................................................. 46
5.2.11 MR18 –Autonegotiation Register B Bit Descriptions.............................................................................. 46
5.2.12 MR20 –User Defined Register Bit Descriptions...................................................................................... 46
5.2.13 MR21 –RXER Counter Register Bit Descriptions................................................................................... 47
5.2.14 MR28 –Device-Specific Register 1 (Status Register) Bit Descriptions..................................................... 47
5.2.15 MR29 –Device-Specific Register 2 (100Mbps Control) Bit Descriptions................................................. 48
5.2.16 MR30 –Device-Specific Register 3 (10Mbps Control) Bit Descriptions................................................... 49
5.2.17 MR31 –Device-Specific Register 4 (Quick Status) Bit Descriptions........................................................ 50
6.0 CPU I/O READ AND WRITE FUNCTIONS................................................................................................. 51
6.1 ISA
BUS TYPE ACCESS FUNCTIONS
. ................................................................................................................... 51
6.2 80186 CPU
BUS TYPE ACCESS FUNCTIONS
......................................................................................................... 51
6.3 MC68K CPU
BUS TYPE ACCESS FUNCTIONS
...................................................................................................... 52
6.4 MCS-51 CPU
BUS TYPE ACCESS FUNCTIONS
..................................................................................................... 52
6.5 CPU A
CCESS
MII S
TATION
M
ANAGEMENT FUNCTIONS
. .................................................................................... 53
7.0 ELECTRICAL SPECIFICATION AND TIMINGS....................................................................................... 54
7.1 A
BSOLUTE
M
AXIMUM
R
ATINGS
........................................................................................................................ 54
7.2 G
ENERAL
O
PERATION
C
ONDITIONS
................................................................................................................... 54
7.3 DC C
HARACTERISTICS
..................................................................................................................................... 54
7.4 A.C. T
IMING
C
HARACTERISTICS
....................................................................................................................... 55
7.4.1 XTAL / CLOCK........................................................................................................................................ 55
7.4.2 Reset Timing............................................................................................................................................ 55
7.4.3 ISA Bus Access Timing............................................................................................................................. 57
7.4.4 80186 Type I/O Access Timing................................................................................................................. 58
7.4.5 68K Type I/O Access Timing.................................................................................................................... 59
7.4.6 8051 Bus Access Timing........................................................................................................................... 60
7.4.7 MII Timing............................................................................................................................................... 61
8.0 PACKAGE INFORMATION........................................................................................................................... 62
APPENDIX A: APPLICATION NOTE 1............................................................................................................. 63
A.1 U
SING
C
RYSTAL
25MH
Z
................................................................................................................ 63
A.2 U
SING
O
SCILLATOR
25MH
Z
......................................................................................................... 63
APPENDIX B: POWER CONSUMPTION REFERENCE DATA...................................................................... 64
ERRATA OF AX88796 .......................................................................................................................................... 65
DEMONSTRATION CIRCUIT (A) : AX88796 WITH ISA BUS + HOMEPNA 1M8 PHY.............................. 66
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