186
32133D–11/2011
UC3D
14.6.1
Control Register
Name:
CR
Access Type:
Read/Write
Offset:
0x00
Reset Value:
0x00000000
When the SR.BUSY bit is set, writes to this register will be discarded and this register will read as zero.
PSEL: Prescaler Select
Selects prescaler bit PSEL as source clock for the counter.
CAn: Clear on Alarm n
0: The corresponding alarm will not clear the counter.
1: The corresponding alarm will clear the counter.
CAL: Calendar Mode
0: The AST operates in counter mode.
1: The AST operates in calendar mode.
PCLR: Prescaler Clear
Writing a zero to this bit has no effect.
Writing a one to this bit clears the prescaler.
This bit always reads as zero.
EN: Enable
0: The AST is disabled.
1: The AST is enabled.
31
30
29
28
27
26
25
24
-
---
--
23
22
21
20
19
18
17
16
-
PSEL
15
14
13
12
11
10
9
8
-
---
--
CA1
CA0
76
543
21
0
-
CAL
PCLR
EN