231
32133D–11/2011
UC3D
16.7.10
Test Register
Name:
TEST
Access Type:
Read/Write
Offset:
0x024
Reset Value:
0x00000000
TESTEN: Test Enable
0: This bit disables external interrupt test mode.
1: This bit enables external interrupt test mode.
INTn: External Interrupt n
Writing a zero to this bit will set the input value to INTn to zero, if test mode is enabled.
Writing a one to this bit will set the input value to INTn to one, if test mode is enabled.
Please refer to the Module Configuration section for the number of external interrupts.
NMI: Non-Maskable Interrupt
Writing a zero to this bit will set the input value to NMI to zero, if test mode is enabled.
Writing a one to this bit will set the input value to NMI to one, if test mode is enabled.
If TESTEN is 1, the value written to this bit will be the value to the interrupt detector and the value on the pad will be ignored.
31
30
29
28
27
26
25
24
TESTEN
INT30INT29
INT28INT27
INT26INT25
INT24
23
22
21
20
19
18
17
16
INT23
INT22
INT21
INT20
INT19
INT18
INT17
INT16
15
14
13
12
11
10
9
8
INT15
INT14
INT13
INT12
INT11
INT10
INT9
INT8
76
543
21
0
INT7
INT6
INT5
INT4
INT3
INT2
INT1
NMI