
474
32133D鈥�11/2011
UC3D
24. Two-wire Slave Interface (TWIS)
Rev.: 1.2.0.1
24.1 Features
Compatible with IC standard
鈥� Transfer speeds of 100 and 400 kbit/s
鈥� 7 and 10-bit and General Call addressing
Compatible with SMBus standard
鈥� Hardware Packet Error Checking (CRC) generation and verification with ACK response25 ms
clock low timeout delay
鈥� 25 ms slave cumulative clock low extend time
Compatible with PMBus
DMA interface for reducing CPU load
Arbitrary transfer lengths, including 0 data bytes
Optional clock stretching if transmit or receive buffers not ready for data transfer
32-bit Peripheral Bus interface for configuration of the interface
24.2 Overview
The Atmel Two-wire Slave Interface (TWIS) interconnects components on a unique two-wire
bus, made up of one clock line and one data line with speeds of up to 400 kbit/s, based on a
byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus, IC, or
SMBus-compatible master. The TWIS is always a bus slave and can transfer sequential or sin-
gle bytes.
Below,
Table 24-1 lists the compatibility level of the Atmel Two-wire Slave Interface and a full IC
compatible device.
Note:
1. START + b000000001 + Ack + Sr
Below,
Table 24-2 lists the compatibility level of the Atmel Two-wire Slave Interface and a full
SMBus compatible device.
Table 24-1.
Atmel TWIS Compatibility with IC Standard
IC Standard
Atmel TWIS
Standard-mode (100 kbit/s)
Supported
Fast-mode (400 kbit/s)
Supported
7 or 10 bits Slave Addressing
Supported
Not Supported
Repeated Start (Sr) Condition
Supported
ACK and NAK Management
Supported
Slope control and input filtering (Fast mode)
Supported
Clock stretching
Supported
Table 24-2.
Atmel TWIS Compatibility with SMBus Standard
SMBus Standard
Atmel TWIS
Bus Timeouts
Supported
Address Resolution Protocol
Supported
Packet Error Checking
Supported