
24
32003M–AVR32–09/09
AT32AP7000
6.3
Programming Model
6.3.1
Register file configuration
The AVR32B architecture specifies that the exception contexts may have a different number of
in AVR32 AP.
Figure 6-3.
The AVR32 AP Register File
6.3.2
Status register configuration
The Status Register (SR) is splitted into two halfwords, one upper and one lower, see
Figure 6-4code flags and the R, T and L bits, while the upper halfword contains information about the
mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details.
Figure 6-4.
The Status Register High Halfword
Application
Bit 0
Supervisor
Bit 31
PC
SR
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R3
R1
R2
R0
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
RSR_INT0
SR
RSR_EX
SR
SP_APP
SP_SYS
RSR_NMI
SR
R12
R11
R9
R10
R8
Bit 0
Bit 31
PC
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R3
R1
R2
R0
Bit 0
Bit 31
PC
FINTPC
SMPC
R7
R5
R6
R4
R3
R1
R2
R0
Bit 0
Bit 31
PC
LR_INT3
R12_INT3
R11_INT3
R9_INT3
R10_INT3
R8_INT3
SP_SYS
R12
R11
R9
R10
R8
Bit 0
Bit 31
PC
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R3
R1
R2
R0
SP_SYS
R12
R11
R9
R10
R8
Bit 0
Bit 31
PC
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R3
R1
R2
R0
SP_SYS
R12
R11
R9
R10
R8
Bit 0
Bit 31
PC
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R3
R1
R2
R0
SP_SYS
R12
R11
R9
R10
R8
RSR_INT1
SR
RSR_INT2
SR
RSR_INT3
SR
INT0
INT1
INT2
INT3
Exception
NMI
FINTPC
SMPC
R7
R5
R6
R4
R3
R1
R2
R0
R12
R11
R9
R10
R8
LR
RSR_SUP
RAR_INT0
RAR_EX
RAR_NMI
RAR_INT1
RAR_INT2
RAR_INT3
RAR_SUP
Bit 31
0
Bit 16
Interrupt Level 0 Mask
Interrupt Level 1 Mask
Interrupt Level 3 Mask
Interrupt Level 2 Mask
1
0
1
0
Reserved
FE
I0M
GM
M1
J
D
M0
EM
I2M
DM
-
M2
LC
1
-
Initial value
Bit name
I1M
Mode Bit 0
Mode Bit 1
H
Mode Bit 2
Reserved
Debug State
-
I3M
Java State
Exception Mask
Global Interrupt Mask
Debug State Mask
Java Handle
Reserved