
PIC16F946
DS41265A-page 182
Preliminary
2005 Microchip Technology Inc.
FIGURE 14-12:
CLOCK SYNCHRONIZATION TIMING
TABLE 14-4:
REGISTERS ASSOCIATED WITH I2C OPERATION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
Resets
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0Ch
PIR1
EEIF
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000
0000 0000
8Ch
PIE1
EEIE
ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000
0000 0000
13h
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
14h
SSPCON
WCOL SSPOV SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0
0000 0000
87h
TRISC
PORTC Data Direction Register
1111 1111
93h
SSPADD Synchronous Serial Port (I2C mode) Address Register
0000 0000
94h
SSPSTAT SMP(1) CKE(1)
D/A
PS
R/W
UA
BF
0000 0000
Legend:
x
= unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by SSP
module in I2C mode.
Note 1:
Maintain these bits clear in I2C mode.
SDA
SCL
DX-1
DX
WR
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSPCON
CKP
Master device
deasserts clock
Master device
asserts clock