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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ATMEGA169PV-8MCU
寤犲晢锛� Atmel
鏂囦欢闋佹暩(sh霉)锛� 36/274闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� MCU AVR 16K ISP FLASH 8MHZ 64QFN
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� megaAVR Introduction
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 260
绯诲垪锛� AVR® ATmega
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 8-浣�
閫熷害锛� 8MHz
閫i€氭€э細 SPI锛孶ART/USART锛孶SI
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯/寰�(f霉)浣�锛孡CD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 54
绋嬪簭瀛樺劜鍣ㄥ閲忥細 16KB锛�8K x 16锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶у皬锛� 512 x 8
RAM 瀹归噺锛� 1K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.8 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 64-VQFN 闆欐帓瑁搁湶鐒婄洡
鍖呰锛� 鎵樼洡
閰嶇敤锛� ATSTK600-TQFP64-ND - STK600 SOCKET/ADAPTER 64-TQFP
ATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM
ATJTAGICE2-ND - AVR ON-CHIP D-BUG SYSTEM
ATAVRBFLY-ND - KIT EVALUATION AVR BUTTERFLY
ATSTK502-ND - MOD EXPANSION AVR STARTER 500
ATSTK500-ND - PROGRAMMER AVR STARTER KIT
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130
8018P鈥揂VR鈥�08/10
ATmega169P
Note:
1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the
WGM12:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
15.11.2
TCCR1B 鈥� Timer/Counter1 Control Register B
Bit 7 鈥� ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four
successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
Bit 6 鈥� ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture
event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.
Table 15-4.
Waveform Generation Mode Bit Description(1)
Mode
WGM13
WGM12
(CTC1)
WGM11
(PWM11)
WGM10
(PWM10)
Timer/Counter Mode of
Operation
TOP
Update of
OCR1
x at
TOV1 Flag
Set on
0
Normal
0xFFFF
Immediate
MAX
1
0
1
PWM, Phase Correct, 8-bit
0x00FF
TOP
BOTTOM
2
0
1
0
PWM, Phase Correct, 9-bit
0x01FF
TOP
BOTTOM
3
0
1
PWM, Phase Correct, 10-bit
0x03FF
TOP
BOTTOM
4
0
1
0
CTC
OCR1A
Immediate
MAX
5
0
1
0
1
Fast PWM, 8-bit
0x00FF
BOTTOM
TOP
6
0
1
0
Fast PWM, 9-bit
0x01FF
BOTTOM
TOP
7
0
1
Fast PWM, 10-bit
0x03FF
BOTTOM
TOP
8
100
0
PWM, Phase and Frequency
Correct
ICR1
BOTTOM
9
100
1
PWM, Phase and Frequency
Correct
OCR1A
BOTTOM
10
1
0
1
0
PWM, Phase Correct
ICR1
TOP
BOTTOM
11
1
0
1
PWM, Phase Correct
OCR1A
TOP
BOTTOM
12
1
0
CTC
ICR1
Immediate
MAX
13
1
0
1
(Reserved)
鈥�
14
1
0
Fast PWM
ICR1
BOTTOM
TOP
15
1
Fast PWM
OCR1A
BOTTOM
TOP
Bit
765
4
3
210
(0x81)
ICNC1
ICES1
鈥�
WGM13
WGM12
CS12
CS11
CS10
TCCR1B
Read/Write
R/W
R
R/W
Initial Value
0
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
ATMEGA169P-16MCU MCU AVR 16K ISP FLSH 16MHZ 64QFN
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