TABLE 19-14: I2" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ATMEGA169PV-8MCU
寤犲晢锛� Atmel
鏂囦欢闋佹暩(sh霉)锛� 173/274闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� MCU AVR 16K ISP FLASH 8MHZ 64QFN
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� megaAVR Introduction
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 260
绯诲垪锛� AVR® ATmega
鏍稿績铏曠悊鍣細 AVR
鑺珨灏哄锛� 8-浣�
閫熷害锛� 8MHz
閫ｉ€氭€э細 SPI锛孶ART/USART锛孶SI
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯/寰�(f霉)浣�锛孡CD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 54
绋嬪簭瀛樺劜鍣ㄥ閲忥細 16KB锛�8K x 16锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 512 x 8
RAM 瀹归噺锛� 1K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 1.8 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 8x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 64-VQFN 闆欐帓瑁搁湶鐒婄洡
鍖呰锛� 鎵樼洡
閰嶇敤锛� ATSTK600-TQFP64-ND - STK600 SOCKET/ADAPTER 64-TQFP
ATAVRISP2-ND - PROGRAMMER AVR IN SYSTEM
ATJTAGICE2-ND - AVR ON-CHIP D-BUG SYSTEM
ATAVRBFLY-ND - KIT EVALUATION AVR BUTTERFLY
ATSTK502-ND - MOD EXPANSION AVR STARTER 500
ATSTK500-ND - PROGRAMMER AVR STARTER KIT
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�绗�11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�绗�22闋�绗�23闋�绗�24闋�绗�25闋�绗�26闋�绗�27闋�绗�28闋�绗�29闋�绗�30闋�绗�31闋�绗�32闋�绗�33闋�绗�34闋�绗�35闋�绗�36闋�绗�37闋�绗�38闋�绗�39闋�绗�40闋�绗�41闋�绗�42闋�绗�43闋�绗�44闋�绗�45闋�绗�46闋�绗�47闋�绗�48闋�绗�49闋�绗�50闋�绗�51闋�绗�52闋�绗�53闋�绗�54闋�绗�55闋�绗�56闋�绗�57闋�绗�58闋�绗�59闋�绗�60闋�绗�61闋�绗�62闋�绗�63闋�绗�64闋�绗�65闋�绗�66闋�绗�67闋�绗�68闋�绗�69闋�绗�70闋�绗�71闋�绗�72闋�绗�73闋�绗�74闋�绗�75闋�绗�76闋�绗�77闋�绗�78闋�绗�79闋�绗�80闋�绗�81闋�绗�82闋�绗�83闋�绗�84闋�绗�85闋�绗�86闋�绗�87闋�绗�88闋�绗�89闋�绗�90闋�绗�91闋�绗�92闋�绗�93闋�绗�94闋�绗�95闋�绗�96闋�绗�97闋�绗�98闋�绗�99闋�绗�100闋�绗�101闋�绗�102闋�绗�103闋�绗�104闋�绗�105闋�绗�106闋�绗�107闋�绗�108闋�绗�109闋�绗�110闋�绗�111闋�绗�112闋�绗�113闋�绗�114闋�绗�115闋�绗�116闋�绗�117闋�绗�118闋�绗�119闋�绗�120闋�绗�121闋�绗�122闋�绗�123闋�绗�124闋�绗�125闋�绗�126闋�绗�127闋�绗�128闋�绗�129闋�绗�130闋�绗�131闋�绗�132闋�绗�133闋�绗�134闋�绗�135闋�绗�136闋�绗�137闋�绗�138闋�绗�139闋�绗�140闋�绗�141闋�绗�142闋�绗�143闋�绗�144闋�绗�145闋�绗�146闋�绗�147闋�绗�148闋�绗�149闋�绗�150闋�绗�151闋�绗�152闋�绗�153闋�绗�154闋�绗�155闋�绗�156闋�绗�157闋�绗�158闋�绗�159闋�绗�160闋�绗�161闋�绗�162闋�绗�163闋�绗�164闋�绗�165闋�绗�166闋�绗�167闋�绗�168闋�绗�169闋�绗�170闋�绗�171闋�绗�172闋�鐣�(d膩ng)鍓嶇173闋�绗�174闋�绗�175闋�绗�176闋�绗�177闋�绗�178闋�绗�179闋�绗�180闋�绗�181闋�绗�182闋�绗�183闋�绗�184闋�绗�185闋�绗�186闋�绗�187闋�绗�188闋�绗�189闋�绗�190闋�绗�191闋�绗�192闋�绗�193闋�绗�194闋�绗�195闋�绗�196闋�绗�197闋�绗�198闋�绗�199闋�绗�200闋�绗�201闋�绗�202闋�绗�203闋�绗�204闋�绗�205闋�绗�206闋�绗�207闋�绗�208闋�绗�209闋�绗�210闋�绗�211闋�绗�212闋�绗�213闋�绗�214闋�绗�215闋�绗�216闋�绗�217闋�绗�218闋�绗�219闋�绗�220闋�绗�221闋�绗�222闋�绗�223闋�绗�224闋�绗�225闋�绗�226闋�绗�227闋�绗�228闋�绗�229闋�绗�230闋�绗�231闋�绗�232闋�绗�233闋�绗�234闋�绗�235闋�绗�236闋�绗�237闋�绗�238闋�绗�239闋�绗�240闋�绗�241闋�绗�242闋�绗�243闋�绗�244闋�绗�245闋�绗�246闋�绗�247闋�绗�248闋�绗�249闋�绗�250闋�绗�251闋�绗�252闋�绗�253闋�绗�254闋�绗�255闋�绗�256闋�绗�257闋�绗�258闋�绗�259闋�绗�260闋�绗�261闋�绗�262闋�绗�263闋�绗�264闋�绗�265闋�绗�266闋�绗�267闋�绗�268闋�绗�269闋�绗�270闋�绗�271闋�绗�272闋�绗�273闋�绗�274闋�
PIC16F946
DS41265A-page 252
Preliminary
2005 Microchip Technology Inc.
TABLE 19-14: I2C BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max
Units
Conditions
100*
THIGH
Clock high time
100 kHz mode
4.0
鈥�
渭s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
鈥�
渭s
Device must operate at a
minimum of 10 MHz
SSP Module
1.5TCY
鈥�
101*
TLOW
Clock low time
100 kHz mode
4.7
鈥�
渭s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
鈥�
渭s
Device must operate at a
minimum of 10 MHz
SSP Module
1.5TCY
鈥�
102*
TR
SDA and SCL rise
time
100 kHz mode
鈥�
1000
ns
400 kHz mode
20 + 0.1CB
300
ns
CB is specified to be from
10-400 pF
103*
TF
SDA and SCL fall
time
100 kHz mode
鈥�
300
ns
400 kHz mode
20 + 0.1CB
300
ns
CB is specified to be from
10-400 pF
90*
TSU:STA
Start condition
setup time
100 kHz mode
4.7
鈥�
渭s
Only relevant for
Repeated Start condition
400 kHz mode
0.6
鈥�
渭s
91*
THD:STA
Start condition hold
time
100 kHz mode
4.0
鈥�
渭s
After this period the first
clock pulse is generated
400 kHz mode
0.6
鈥�
渭s
106*
THD:DAT
Data input hold time 100 kHz mode
0
鈥�
ns
400 kHz mode
0
0.9
渭s
107*
TSU:DAT
Data input setup
time
100 kHz mode
250
鈥�
ns
(Note 2)
400 kHz mode
100
鈥�
ns
92*
TSU:STO
Stop condition
setup time
100 kHz mode
4.7
鈥�
渭s
400 kHz mode
0.6
鈥�
渭s
109*
TAA
Output valid from
clock
100 kHz mode
鈥�
3500
ns
(Note 1)
400 kHz mode
鈥�
ns
110*
TBUF
Bus free time
100 kHz mode
4.7
鈥�
渭s
Time the bus must be free
before a new transmission
can start
400 kHz mode
1.3
鈥�
渭s
CB
Bus capacitive loading
鈥�
400
pF
*
These parameters are characterized but not tested.
Note 1:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2:
A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the
requirement TSU:DAT
鈮� 250 ns must then be met. This will automatically be the case if the device does not
stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it
must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I2C bus specification), before the SCL line is released.
鐩搁棞(gu膩n)PDF璩囨枡
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
ATMEGA169PV-8MU 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU AVR 16K FLASH 512B EE 1K SRAM 5V RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
ATMEGA169PV-8MU SL383 鍒堕€犲晢:Atmel Corporation 鍔熻兘鎻忚堪:MCU 8BIT ATMEGA RISC 16KB FLASH 2.5V/3.3V/5V 64PIN MLF - Tape and Reel
ATMEGA169PV-8MU 鍒堕€犲晢:Atmel Corporation 鍔熻兘鎻忚堪:IC 8BIT MCU AVR MEGA 8MHZ 64-QFN
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ATMEGA169V 鍒堕€犲晢:ATMEL 鍒堕€犲晢鍏ㄧū:ATMEL Corporation 鍔熻兘鎻忚堪:8-bit Microcontroller with 16K Bytes In-System Programmable Flash
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