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參數(shù)資料
| 型號： | ATF1508ASVL-20JI84 |
| 廠商： | ATMEL CORP |
| 元件分類： | PLD |
| 英文描述： | Highperformance EE PLD |
| 中文描述： | EE PLD, 20 ns, PQCC84 |
| 封裝： | PLASTIC, MS-018AF, LCC-84 |
| 文件頁數(shù)： | 13/22頁 |
| 文件大?。?/td> | 519K |
| 代理商： | ATF1508ASVL-20JI84 |
ATF1508ASV(L)
13
JTAG-BST Overview
The JTAG-BST (JTAG boundary-scan testing) is controlled
by the Test Access Port (TAP) controller in the
ATF1508ASV(L). The boundary-scan technique involves
the inclusion of a shift-register stage (contained in a bound-
ary-scan cell) adjacent to each component so that signals
at component boundaries can be controlled and observed
using scan testing principles. Each input pin and I/O pin
has its own Boundary-scan Cell (BSC) in order to support
boundary-scan testing. The ATF1508ASV(L) does not cur-
rently include a Test Reset (TRST) input pin because the
TAP controller is automatically reset at power-up. The six
JTAG-BST modes supported include: SAMPLE/PRE-
LOAD, EXTEST, BYPASS and IDCODE. BST on the
ATF1508ASV(L) is implemented using the Boundary-scan
Definition Language (BSDL) described in the JTAG specifi-
cation (IEEE Standard 1149.1). Any third-party tool that
supports the BSDL format can be used to perform BST on
the ATF1508ASV(L).
The ATF1508ASV(L) also has the option of using four
JTAG-standard I/O pins for in-system programming (ISP).
The ATF1508ASV(L) is programmable through the four
JTAG pins using programming-compatible with the IEEE
JTAG Standard 1149.1. Programming is performed by
using 5V TTL-level programming signals from the JTAG
ISP interface. The JTAG feature is a programmable option.
If JTAG (BST or ISP) is not needed, then the four JTAG
control pins are available as I/O pins.
JTAG Boundary-scan Cell (BSC)
Testing
The ATF1508ASV(L) contains up to 96 I/O pins and four
input pins, depending on the device type and package type
selected. Each input pin and I/O pin has its own boundary-
scan cell (BSC) in order to support boundary-scan testing
as described in detail by IEEE Standard 1149.1. A typical
BSC consists of three capture registers or scan registers
and up to two update registers. There are two types of
BSCs, one for input or I/O pin, and one for the macrocells.
The BSCs in the device are chained together through the
(BST) capture registers. Input to the capture register chain
is fed in from the TDI pin while the output is directed to the
TDO pin. Capture registers are used to capture active
device data signals, to shift data in and out of the device
and to load data into the update registers. Control signals
are generated internally by the JTAG TAP controller. The
BSC configuration for the input and I/O pins and macrocells
are shown below.
BSC Configuration Pins and
Macrocells (Except JTAG TAP Pins)
Note:
The ATF1508ASV(L) has pull-up option on TMS and TDI
pins. This feature is selected as a design option.
Boundary-scan Definition Language
(BSDL) Models for the ATF1508
These are now available in all package types via the Atmel
web site. These models can be used for Boundary-scan
Test Operation in the ATF1508ASV(L) and have been
scheduled to conform to the IEEE 1149.1 standard.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ATF1508ASVL-20QI100 | Highperformance EE PLD |
| ATF1508AS | CAP POLYPROPYLENE .062UF 50V 1% |
| ATF1508ASZ | Hex Buffer/Driver With Open-Drain Outputs 14-SSOP -40 to 85 |
| ATF1508ASV(L) | ATF1508ASV(L) [Updated 9/02. 23 Pages] 128 Macrcells with ISP. 3-volt and low power |
| ATF1508AEL-15 | Circular Connector; No. of Contacts:6; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:11; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:11-98 RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATF1508ASVL-20JU84 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 128 MACROCELL 3.3V 20NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508ASVL-20QC100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 128 MACROCELL w/ISP LO-PWR 3.3V-20NS RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508ASVL-20QC160 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 128 MACROCELL w/ISP LO-PWR 3.3V-20NS RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508ASVL-20QI100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 128 MACROCELL 3.3V 20NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508ASVL-20QI160 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 128 MACROCELL 3.3V 20NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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