- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381525 > ATF1508ASVL-20JI84 (ATMEL CORP) Highperformance EE PLD PDF資料下載
參數(shù)資料
| 型號： | ATF1508ASVL-20JI84 |
| 廠商： | ATMEL CORP |
| 元件分類： | PLD |
| 英文描述： | Highperformance EE PLD |
| 中文描述： | EE PLD, 20 ns, PQCC84 |
| 封裝： | PLASTIC, MS-018AF, LCC-84 |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 519K |
| 代理商： | ATF1508ASVL-20JI84 |
ATF1508ASV(L)
12
Power-down Mode
The ATF1508ASV(L) includes two pins for optional pin-
controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the
PD1 and PD2 pin is high, the device supply current is
reduced to less than 5 mA. During power-down, all output
data and internal logic states are latched and held. There-
fore, all registered and combinatorial output data remain
valid. Any outputs that were in a high-Z state at the onset
will remain at high-Z. During power-down, all input signals
except the power-down pin are blocked. Input and I/O hold
latches remain active to ensure that pins do not float to
indeterminate levels, further reducing system power. The
power-down pin feature is enabled in the logic design file.
Designs using either power-down pin may not use the PD
pin logic array input. However, buried logic resources in
this macrocell may still be used.
Notes:
1. For slow slew outputs, add t
SSO
.
2. Pin or product term.
Power Down AC Characteristics
(1)(2)
Symbol
Parameter
-15
-20
Units
Min
Max
Min
Max
t
IVDH
Valid I, I/O before PD High
15
20
ns
t
GVDH
Valid OE
(2)
before PD High
15
20
ns
t
CVDH
Valid Clock
(2)
before PD High
15
20
ns
t
DHIX
I, I/O Don
’
t Care after PD High
25
30
ns
t
DHGX
OE
(2)
Don
’
t Care after PD High
25
30
ns
t
DHCX
Clock
(2)
Don
’
t Care after PD High
25
30
ns
t
DLIV
PD Low to Valid I, I/O
1
1
μs
t
DLGV
PD Low to Valid OE (Pin or Term)
1
1
μs
t
DLCV
PD Low to Valid Clock (Pin or Term)
1
1
μs
t
DLOV
PD Low to Valid Output
1
1
μs
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ATF1508ASVL-20QI100 | Highperformance EE PLD |
| ATF1508AS | CAP POLYPROPYLENE .062UF 50V 1% |
| ATF1508ASZ | Hex Buffer/Driver With Open-Drain Outputs 14-SSOP -40 to 85 |
| ATF1508ASV(L) | ATF1508ASV(L) [Updated 9/02. 23 Pages] 128 Macrcells with ISP. 3-volt and low power |
| ATF1508AEL-15 | Circular Connector; No. of Contacts:6; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:11; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:11-98 RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATF1508ASVL-20JU84 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 128 MACROCELL 3.3V 20NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508ASVL-20QC100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 128 MACROCELL w/ISP LO-PWR 3.3V-20NS RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508ASVL-20QC160 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 128 MACROCELL w/ISP LO-PWR 3.3V-20NS RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508ASVL-20QI100 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 128 MACROCELL 3.3V 20NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1508ASVL-20QI160 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 128 MACROCELL 3.3V 20NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。