參數(shù)資料
型號: AT90S8535-8JI
廠商: Atmel
文件頁數(shù): 65/127頁
文件大小: 0K
描述: IC MCU 8K 8MHZ A/D IT 44PLCC
標(biāo)準(zhǔn)包裝: 27
系列: AVR® 90S
核心處理器: AVR
芯體尺寸: 8-位
速度: 8MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 8KB(4K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 512 x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4 V ~ 6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 管件
PIC16C71X
DS30272A-page 42
1997 Microchip Technology Inc.
7.4
A/D Conversions
Example 7-2 shows how to perform an A/D conversion.
The RA pins are congured as analog inputs. The ana-
log reference (VREF) is the device VDD. The A/D inter-
rupt is enabled, and the A/D conversion clock is FRC.
The conversion is performed on the RA0 pin (channel
0).
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRES register will
NOT be updated with the partially completed A/D con-
version sample. That is, the ADRES register will con-
tinue to contain the value of the last completed
conversion (or the last value written to the ADRES reg-
ister). After the A/D conversion is aborted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, an acquisition is automatically started
on the selected channel.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
EXAMPLE 7-2:
A/D CONVERSION
BSF
STATUS, RP0
; Select Bank 1
CLRF
ADCON1
; Configure A/D inputs
BCF
STATUS, RP0
; Select Bank 0
MOVLW
0xC1
; RC Clock, A/D is on, Channel 0 is selected
MOVWF
ADCON0
;
BSF
INTCON, ADIE
; Enable A/D Interrupt
BSF
INTCON, GIE
; Enable all interrupts
;
Ensure that the required sampling time for the selected input channel has elapsed.
;
Then the conversion may be started.
;
BSF
ADCON0, GO
; Start A/D Conversion
:
; The ADIF bit will be set and the GO/DONE bit
:
;
is cleared upon completion of the A/D Conversion.
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