參數資料
| 型號： | AT90S8535-8JI |
| 廠商： | Atmel |
| 文件頁數： | 49/127頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8K 8MHZ A/D IT 44PLCC |
| 標準包裝： | 27 |
| 系列： | AVR® 90S |
| 核心處理器： | AVR |
| 芯體尺寸： | 8-位 |
| 速度： | 8MHz |
| 連通性： | SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，POR，PWM，WDT |
| 輸入/輸出數： | 32 |
| 程序存儲器容量： | 8KB（4K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 512 x 8 |
| RAM 容量： | 512 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4 V ~ 6 V |
| 數據轉換器： | A/D 8x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
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28
AT90S/LS8535
1041H–11/01
Bit 5 – ICF1: Input Capture Flag 1
The ICF1 bit is set (one) to flag an input capture event, indicating that the
Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1
is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ICF1 is cleared by writing a logical “1” to the flag. When the SREG I-bit
and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the
Timer/Counter1 Capture Interrupt is executed.
Bit 4 – OCF1A: Output Compare Flag 1A
The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1
and the data in OCR1A (Output Compare Register 1A). OCF1A is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1A is
cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1A
(Timer/Counter1 Compare Match InterruptA Enable) and the OCF1A are set (one), the
Timer/Counter1 Compare A Match Interrupt is executed.
Bit 3 – OCF1B: Output Compare Flag 1B
The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1
and the data in OCR1B (Output Compare Register 1B). OCF1B is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, OCF1B is
cleared by writing a logical “1” to the flag. When the I-bit in SREG and OCIE1B
(Timer/Counter1 Compare Match InterruptB Enable) and the OCF1B are set (one), the
Timer/Counter1 Compare Match B Interrupt is executed.
Bit 2 – TOV1: Timer/Counter1 Overflow Flag
The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV1 is cleared by writing a logical “1” to the flag. When the I-bit in SREG and TOIE1
(T i m er /Counter 1 O v erfl ow Inte rr upt Enabl e) and T OV 1 ar e s e t ( one ), the
Timer/Counter1 Overflow Interrupt is executed. In up/down PWM mode, this bit is set
when Timer/Counter1 advances from $0000.
Bit 1 – Res: Reserved Bit
This bit is a reserved bit in the AT90S8535 and always reads zero.
Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared
by hardware when executing the corresponding interrupt handling vector. Alternatively,
TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit and TOIE0
(T i m er /Counter 0 O v erfl ow Inte rr upt Enabl e) and T OV 0 ar e s e t ( one ), the
Timer/Counter0 Overflow Interrupt is executed. In up/down PWM mode, this bit is set
when Timer/Counter1 advances from $0000.
External Interrupts
The external interrupts are triggered by the INT1 and INT0 pins. Observe that, if
enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs.
This feature provides a way of generating a software interrupt. The external interrupts
can be triggered by a falling or rising edge or a low level. This is set up as indicated in
the specification for the MCU Control Register (MCUCR). When the external interrupt is
enabled and is configured as level-triggered, the interrupt will trigger as long as the pin
is held low.
The external interrupts are set up as described in the specification for the MCU Control
Register (MCUCR).
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