參數(shù)資料
型號: AT89C51RD2-SLRUM
廠商: Atmel
文件頁數(shù): 108/137頁
文件大小: 0K
描述: IC MCU FLASH 8051 EEP 64K 44PLCC
產(chǎn)品培訓模塊: MCU Product Line Introduction
標準包裝: 1
系列: 89C
核心處理器: 8051
芯體尺寸: 8-位
速度: 60MHz
連通性: SPI,UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-LCC(J 形引線)
包裝: 標準包裝
配用: AT89OCD-01-ND - USB EMULATOR FOR AT8XC51 MCU
AT89STK-11-ND - KIT STARTER FOR AT89C51RX2
其它名稱: AT89C51RD2-SLRUMDKR
72
4235K–8051–05/08
AT89C51RD2/ED2
17. Interrupt System
The AT89C51RD2/ED2 has a total of 9 interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard
interrupt and the PCA global interrupt. These interrupts are shown in Figure 17-1.
Figure 17-1. Interrupt Control System
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit
in the Interrupt Enable register (Table 17-4 and Table 17-6). This register also contains a global
disable bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by
setting or clearing a bit in the Interrupt Priority register (Table 17-7) and in the Interrupt Priority
High register (Table 17-5 and Table 17-6) shows the bit values and priority levels associated
with each combination.
IE1
0
3
High Priority
Interrupt
Polling
Sequence, Decreasing from
High to Low Priority
Low Priority
Interrupt
Global Disable
Individual Enable
EXF2
TF2
TI
RI
TF0
INT0
INT1
TF1
IPH, IPL
IE0
0
3
0
3
0
3
0
3
0
3
0
3
PCA IT
KBD IT
SPI IT
0
3
0
3
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