參數(shù)資料
型號： AT89C5131A-RDTUM
廠商： Atmel
文件頁數(shù)： 31/176頁
文件大?。?/td> 0K
描述： IC 8051 MCU FLASH 32K USB 64VQFP
產(chǎn)品培訓模塊： MCU Product Line Introduction
標準包裝： 800
系列： AT89C513x
核心處理器： C52X2
芯體尺寸： 8-位
速度： 48MHz
連通性： I²C，SPI，UART/USART，USB
外圍設備： LED，POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 1.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-LQFP
包裝： 托盤
配用： AT89STK-10-ND - KIT EVAL APPL MASS STORAGE
AT89STK-05-ND - KIT STARTER FOR AT89C5131
124
AT89C5131
4136C–USB–04/05
Bulk/Interrupt IN Transactions
in Ping-pong Mode
Figure 62. Bulk/Interrupt IN Transactions in Ping-pong Mode
An endpoint will be first enabled and configured before being able to send Bulk or Inter-
rupt packets.
The firmware will fill the FIFO bank 0 with the data to be sent and set the TXRDY bit in
the UEPSTAX register to allow the USB controller to send the data stored in FIFO at the
next IN request concerning the endpoint. The FIFO banks are automatically switched,
and the firmware can immediately write into the endpoint FIFO bank 1.
When the IN packet concerning the bank 0 has been sent and acknowledged by the
Host, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if
enabled. The firmware will clear the TXCMPL bit before filling the endpoint FIFO bank 0
with new data. The FIFO banks are then automatically switched.
When the IN packet concerning the bank 1 has been sent and acknowledged by the
Host, the TXCMPL bit is set by the USB controller. This triggers a USB interrupt if
enabled. The firmware will clear the TXCMPL bit before filling the endpoint FIFO bank 1
with new data.
The bank switch is performed by the USB controller each time the TXRDY bit is set by
the firmware. Until the TXRDY bit has been set by the firmware for an endpoint bank,
the USB controller will answer a NAK handshake for each IN requests concerning this
bank.
Note that in the example above, the firmware clears the Transmit Complete bit (TXC-
MPL) before setting the Transmit Ready bit (TXRDY). This is done in order to avoid the
firmware to clear at the same time the TXCMPL bit for bank 0 and the bank 1.
The firmware will never write more bytes than supported by the endpoint FIFO.
IN
DATA0 (n Bytes)
ACK
HOST
UFI
C51
Endpoint FIFO Bank 0 - Write Byte 1
IN
NACK
TXCMPL
Endpoint FIFO Bank 0 - Write Byte 2
Endpoint FIFO Bank 0 - Write Byte n
Set TXRDY
Endpoint FIFO Bank 1 - Write Byte 1
Endpoint FIFO Bank 1 - Write Byte 2
Endpoint FIFO Bank 1 - Write Byte m
Set TXRDY
IN
DATA1 (m Bytes)
ACK
Endpoint FIFO Bank 0 - Write Byte 1
Endpoint FIFO Bank 0 - Write Byte 2
Endpoint FIFO Bank 0 - Write Byte p
Set TXRDY
Clear TXCMPL
IN
DATA0 (p Bytes)
ACK
TXCMPL
Clear TXCMPL
Endpoint FIFO Bank 1 - Write Byte 1
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相關代理商/技術參數(shù)
參數(shù)描述
AT89C5131A-RDTUM 制造商:Atmel Corporation 功能描述:IC 8BIT MCU C51/C251 48MHZ 64-VQFP
AT89C5131A-S3SIL 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Flash Microcontroller with Full Speed USB Device
AT89C5131A-S3SIM 功能描述:IC 8051 MCU FLASH 32K USB 52PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:AT89C513x 標準包裝:1,500 系列:AVR® ATtiny 核心處理器:AVR 芯體尺寸:8-位 速度:16MHz 連通性:I²C，LIN，SPI，UART/USART，USI 外圍設備:欠壓檢測/復位，POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):16 程序存儲器容量:8KB（4K x 16） 程序存儲器類型:閃存 EEPROM 大小:512 x 8 RAM 容量:512 x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 11x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:帶卷 (TR)
AT89C5131A-S3SUL 功能描述:8位微控制器 -MCU 32K Flash 3V USB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
AT89C5131A-S3SUM 功能描述:8位微控制器 -MCU 32K Flash USB Ind 5V RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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