參數(shù)資料
型號: AT89C5131A-RDTUM
廠商: Atmel
文件頁數(shù): 168/176頁
文件大?。?/td> 0K
描述: IC 8051 MCU FLASH 32K USB 64VQFP
產(chǎn)品培訓模塊: MCU Product Line Introduction
標準包裝: 800
系列: AT89C513x
核心處理器: C52X2
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設備: LED,POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-LQFP
包裝: 托盤
配用: AT89STK-10-ND - KIT EVAL APPL MASS STORAGE
AT89STK-05-ND - KIT STARTER FOR AT89C5131
90
AT89C5131
4136C–USB–04/05
pins (Figure 39). To prevent bus conflicts on the MISO line, only one slave should be
selected at a time by the Master for a transmission.
In a Master configuration, the SS line can be used in conjunction with the MODF flag in
the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin could be used as a general-purpose if the following conditions are met:
The device is configured as a Master and the SSDIS control bit in SPCON is set.
This kind of configuration can be found when only one Master is driving the network
and there is no way that the SS pin could be pulled low. Therefore, the MODF flag in
the SPSTA will never be set(1).
The Device is configured as a Slave with CPHA and SSDIS control bits set(2) This
kind of configuration can happen when the system comprises one Master and one
Slave only. Therefore, the device should always be selected and there is no reason
that the Master uses the SS pin to select the communicating Slave device.
Notes:
1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA =’0’ because in
this mode, the SS is used to start the transmission.
Baud Rate
In Master mode, the baud rate can be selected from a baud rate generator which is con-
trolled by three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is
chosen from one of seven clock rates resulting from the division of the internal clock by
2, 4, 8, 16, 32, 64 or 128.
Table 73 gives the different clock rates selected by SPR2:SPR1:SPR0:
Table 73. SPI Master Baud Rate Selection
SPR2
SPR1
SPR0
Clock Rate
Baud Rate Divisor (BD)
0
Don’t Use
No BRG
001
F
CLK PERIPH/4
4
010
F
CLK PERIPH/8
8
011
F
CLK PERIPH/16
16
100
F
CLK PERIPH/32
32
101
F
CLK PERIPH/64
64
110
F
CLK PERIPH/128
128
1
Don’t Use
No BRG
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