參數(shù)資料
型號： AT89C5131A-RDTIL
廠商： Atmel
文件頁數(shù)： 51/185頁
文件大?。?/td> 0K
描述： IC 8051 MCU FLASH 32K USB 64VQFP
標準包裝： 160
系列： AT89C513x
核心處理器： C52X2
芯體尺寸： 8-位
速度： 48MHz
連通性： I²C，SPI，UART/USART，USB
外圍設備： LED，POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 32KB（32K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 1.25K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-LQFP
包裝： 托盤
配用： AT89STK-10-ND - KIT EVAL APPL MASS STORAGE
AT89STK-05-ND - KIT STARTER FOR AT89C5131
其它名稱： AT89C5131-RDTIL-ND
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70318F-page 144
2008-2012 Microchip Technology Inc.
8.5
Clock Switching Operation
Users can switch applications among any of the four
clock sources (primary, LP, FRC and LPRC) under
software control at any time. To limit the possible side
effects of this flexibility, dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 devices have a safeguard
lock built into the switch process.
8.5.1
ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration
bit in the Configuration register must be programmed to
further details.) If the FCKSM1 Configuration bit is
unprogrammed (‘1’), the clock switching function and
Fail-Safe Clock Monitor function are disabled. This is
the default setting.
The NOSC<2:0> control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is
disabled.
However,
the
COSC<2:0>
bits
(OSCCON<14:12>) reflect the clock source selected
by the FNOSC Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is held at ‘0’ at all
times.
8.5.2
OSCILLATOR SWITCHING SEQUENCE
To perform a clock switch, the following basic sequence
is required:
1.
If required, read the COSC<2:0> bits to determine
the current oscillator source.
2.
Perform the unlock sequence to allow a write to
the OSCCON register high byte.
3.
Write the appropriate value to the NOSC<2:0>
control bits for the new oscillator source.
4.
Perform the unlock sequence to allow a write to
the OSCCON register low byte.
5.
Set the OSWEN bit to initiate the oscillator switch.
After the basic sequence is completed, the system
clock hardware responds as follows:
1.
The clock switching hardware compares the
COSC<2:0> status bits with the new value of the
NOSC<2:0> control bits. If they are the same,
the clock switch is a redundant operation. In this
case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
2.
If a valid clock switch has been initiated, the LOCK
(OSCCON<5>) and the CF (OSCCON<3>) status
bits are cleared.
3.
The new oscillator is turned on by the hardware if
it is not currently running. If a crystal oscillator
must be turned on, the hardware waits until the
Oscillator Start-up Timer (OST) expires. If the new
source is using the PLL, the hardware waits until a
PLL lock is detected (LOCK = 1).
4.
The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
5.
The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the
NOSC<2:0> bit values are transferred to the
COSC<2:0> status bits.
6.
The old clock source is turned off at this time, with
the exception of LPRC (if WDT or FSCM are
enabled).
8.6
Fail-Safe Clock Monitor (FSCM)
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
During an oscillator failure, the FSCM generates a
clock failure trap event and switches the system clock
over to the FRC oscillator. Then, the application
program can either attempt to restart the oscillator or
execute a controlled shutdown. The trap can be treated
as a warm Reset by simply loading the Reset address
into the oscillator fail trap vector.
If the PLL multiplier is used to scale the system clock,
the internal FRC is also multiplied by the same factor
on clock failure. Essentially, the device switches to
FRC with PLL on a clock failure.
Note:
Primary oscillator mode has three different
submodes (XT, HS and EC), which are
determined
by
the
POSCMD<1:0>
Configuration bits. While an application
can switch to and from primary oscillator
mode in software, it cannot switch among
the different primary submodes without
reprogramming the device.
Note 1: The processor continues to execute code
throughout the clock switching sequence.
Timing-sensitive code should not be
executed during this time.
2: Direct clock switches between any pri-
mary oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direc-
tion. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL modes.
3: Refer to Section 42. “Oscillator (Part
IV)” (DS70307) in the “dsPIC33F/PIC24H
Family Reference Manual” for details.
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相關代理商/技術參數(shù)
參數(shù)描述
AT89C5131A-RDTIM 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Flash Microcontroller with Full Speed USB Device
AT89C5131A-RDTUL 功能描述:8位微控制器 -MCU 32K Flash 3V USB RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
AT89C5131A-RDTUM 功能描述:8位微控制器 -MCU C5130A 32K Flash RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
AT89C5131A-RDTUM 制造商:Atmel Corporation 功能描述:IC 8BIT MCU C51/C251 48MHZ 64-VQFP
AT89C5131A-S3SIL 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-bit Flash Microcontroller with Full Speed USB Device
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