參數(shù)資料
型號： ASDP-21365KBCZ-1AA
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： SHARC Processor
中文描述： 16-BIT, 55.55 MHz, OTHER DSP, PBGA136
封裝： MO-205AE, BGA-136
文件頁數(shù)： 38/52頁
文件大小： 1320K
代理商： ASDP-21365KBCZ-1AA
Rev. A
|
Page 38 of 52
|
December 2006
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
SPDIF Transmitter
Serial data input to the SPDIF transmitter can be formatted as
left-justified, I
2
S, or right-justified with word widths of 16, 18,
20, or 24 bits. The following sections provide timing for the
transmitter. This feature is not available on the
ADSP-21363 models.
SPDIF Transmitter—Serial Input Waveforms
Figure 29
shows the right-justified mode. LRCLK is HI for the
left channel and LO for the right channel. Data is valid on the
rising edge of SCLK. The MSB is delayed 12-bit clock periods
(in 20-bit output mode) or 16-bit clock periods (in 16-bit output
mode) from an LRCLK transition, so that when there are
64 SCLK periods per LRCLK period, the LSB of the data will be
right-justified to the next LRCLK transition.
Figure 30
shows the default I
2
S-justified mode. LRCLK is LO for
the left channel and HI for the right channel. Data is valid on the
rising edge of SCLK. The MSB is left-justified to an LRCLK
transition but with a single SCLK period delay.
Figure 31
shows the left-justified mode. LRCLK is HI for the left
channel and LO for the right channel. Data is valid on the rising
edge of SCLK. The MSB is left-justified to an LRCLK transition
with no MSB delay.
Figure 29. Right -Justified Mode
LRCLK
SCLK
SDATA
LEFT CHANNEL
RIGHT CHANNEL
MSB-1
MSB-2
LSB+2 LSB+1
LSB
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
LSB
MSB
Figure 30. I
2
S-Justified Mode
MSB-1
MSB-2
LSB+2 LSB+1
LSB
LRCLK
SCLK
SDATA
LEFTCHANNEL
RIGHTCHANNEL
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB
Figure 31. Left-Justified Mode
LRCLK
SCLK
SDATA
LEFT CHANNEL
RIGHT CHANNEL
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB-1
MSB-2
LSB+2
LSB+1
LSB
MSB
MSB+1
MSB
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