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參數(shù)資料
| 型號(hào)： | ASDP-21365KBCZ-1AA |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | SHARC Processor |
| 中文描述： | 16-BIT, 55.55 MHz, OTHER DSP, PBGA136 |
| 封裝： | MO-205AE, BGA-136 |
| 文件頁數(shù)： | 20/52頁 |
| 文件大小： | 1320K |
| 代理商： | ASDP-21365KBCZ-1AA |
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Rev. A
|
Page 20 of 52
|
December 2006
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Clock Input
Clock Signals
The ADSP-2136x can use an external clock or a crystal. See the
CLKIN pin description in
Table 4 on Page 12
. The user applica-
tion program can configure theADSP-2136x to use its internal
clock generator by connecting the necessary components to the
CLKIN and XTAL pins.
Figure 9
shows the component connec-
tions used for a fundamental frequency crystal operating in
parallel mode.
Note that the clock rate is achieved using a 16.67 MHz crystal
and a PLL multiplier ratio 16:1 (CCLK:CLKIN achieves a clock
speed of 266.72 MHz). To achieve the full core clock rate, pro-
grams need to configure the multiplier bits in the
PMCTL register.
Table 13. Clock Input
Parameter
333 MHz
Unit
Min
Max
Timing Requirements
t
CK
t
CKL
t
CKH
t
CKRF
t
CCLK
2
t
CKJ
3,4
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
CCLK Period
CLKIN Jitter Tolerance
18
1
7.5
1
7.5
1
3.0
1
–250
1
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
2
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CCLK
.
3
Actual input jitter should be combined with ac specifications for accurate timing analysis.
4
Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.
100
ns
ns
ns
ns
ns
ps
3
10
+250
Figure 8. Clock Input
CLKIN
t
CK
t
CKH
t
CKL
t
CKJ
Figure 9. 333 MHz Operation (Fundamental Mode Crystal)
C1
22pF
Y1
R1
1M *
XTAL
CLKIN
C2
22pF
24.576MHz
R2
47 *
R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL
DRIVE POWER. REFER TO CRYSTAL
MANUFACTURER’S SPECIFICATIONS
*TYPICAL VALUES
ADSP-2136X
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