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參數(shù)資料
| 型號(hào)： | AN10E40 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Field Programmable Analog Array |
| 中文描述： | 現(xiàn)場可編程模擬陣列 |
| 文件頁數(shù)： | 28/36頁 |
| 文件大?。?/td> | 293K |
| 代理商： | AN10E40 |
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24
The Analog I/O Cell
The AN10E40 Analog I/O cells are carefully designed to provide robust drive without sacrificing bandwidth figures.
You can see from the plot below that the bandwidth of the I/O cells well exceeds the sort of signals typically
processed within the device.
Min.
Typ.
2 mV
0 dB
20 V/
μ
s
10.8 MHz
Max.
Notes
Input Offset Voltage
Unity Gain
Slew Rate
-3dB Bandwidth
Input Voltage Range
-0.02 dB
+0.02 dB
1 kHz, Sine, 1.0 VRMS
10 k
, 100 pF load
AVSS
AVDD
Pins IOxxZ - When used as a
direct input to the device core cells.
Pins IOxxX and IOxxY - When the
I/O cell is used as a powered input
buffer. (Input range is limited by I/O
buffer output swing limitations.)
Pins IOxxZ - When I/O cell is used
as a powered output buffer.
Pins IOxxX and IOxxY - When I/O
cell is used as a direct output from
a device core cell.
Pins IOxxZ - When I/O cell is used
as a powered output buffer.
Pins IOxxX and IOxxY - When I/O
cell is used as a direct output from
a device core cell.
Input Voltage Range
0.5
AVDD- 0.5
Output Voltage Range
Small Signal Load Defined as:
1 k
|| 100 pF
0.5
AVDD- 0.5
Output Voltage Range
Large Signal Load Defined as:
10 k
|| 100 pF
0.5
AVDD- 0.5
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