參數(shù)資料
型號(hào)： AN10E40
廠商： Electronic Theatre Controls, Inc.
英文描述： Field Programmable Analog Array
中文描述： 現(xiàn)場(chǎng)可編程模擬陣列
文件頁(yè)數(shù)： 20/36頁(yè)
文件大?。?/td> 293K
代理商： AN10E40
16
Configuration Clock
If MODE[2] is held low, a divided down version of the ring oscillator output is used as the configuration logic clock.
CFG_CLK is set to be an output and reflects this clock. If instead MODE[2] is held high, CFG_CLK becomes the
configuration logic clock input. For shortest possible configuration times, use CFG_CLK as an input.
In a minimal system, you may want to take advantage of the AN10E40’s internal ring oscillator. The operating
frequency of the ring oscillator can vary from 10MHz up to 40MHz. This variation is expected and presents no
problems for the proper operation of the configuration engine. The ring oscillator is divided by 8 before use by the
configuration engine.
Figure 19. Block Diagram Showing Clocks and Resets
#
1
2
3
4
5
6
7
Characteristic
CFG_CLK Period
CFG_CLK Low
CFG_CLK High
Ring Osc Period
Ring Osc Low
Ring Osc High
DCLK Period
Min
50
10
10
25
10
10
Always twice the period of
CFG_CLK.
(If MODE[2] = 1 then CFG_CLK is
an input. If MODE[2] = 0, then
CFG_CLK is an output running at
1
/
8
ring oscillator.)
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
50
25
25
100
50
50
the frequency of the internal
Figure 18. Configuration Clock Specifications
2
3
1
5
6
4
7
CFG_CLK (in)
(Internal Ring Osc.)
DCLK (out)
AN10E40
Ring
Oscillator
1/8
0
1
17 Bit APOR Pulse Stretcher
EN
APOR
CLK
Configuration
Engine
POR
CLK
RST
1/2
16
0
F3, PWRUP
MODE[1]
RESETb
DCLK
POR
CFG_CLK
MODE[2]
High_4_BFR
Sys_Rst_Low
SPROM_Clk
Low_4_Int_Clk
Config_Clk
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