- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366551 > AM79C978 (Advanced Micro Devices, Inc.) Single-Chip 1/10 Mbps PCI Home Networking Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C978 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| 中文描述： | 單芯片的1 / 10 Mbps的家庭網(wǎng)絡(luò)控制器的PCI |
| 文件頁(yè)數(shù)： | 43/261頁(yè) |
| 文件大?。?/td> | 3803K |
| 代理商： | AM79C978 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)當(dāng)前第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)
Am79C978
43
ADSTEP (bit 7) in the PCI Command register being
hardwired to 0.
Figure 13.
Bus Acquisition
In burst mode, the deassertion of REQ depends on the
setting of EXTREQ (BCR18, bit 8). If EXTREQ is
cleared to 0, REQ is deasserted at the same time as
FRAME is asserted. (The Am79C978 controller never
performs more than one burst transaction within a sin-
gle bus mastership period.) If EXTREQ is set to 1, the
Am79C978 controller does not deassert REQ until it
starts the last data phase of the transaction.
Once asserted, REQ remains active until GNT has be-
come active and independent of subsequent setting of
STOP (CSR0, bit 2) or SPND (CSR5, bit 0). The asser-
tion of H_RESET or S_RESET, however, will cause
REQ to go inactive immediately.
Bus Master DMA Transfers
There are four primary types of DMA transfers. The
Am79C978 controller uses non-burst as well as burst
cycles for read and write access to the main memory.
Basic Non-Burst Read Transfer
By default, the Am79C978 controller uses non-burst
cycles in all bus master read operations. All controller
non-burst read accesses are of the PCI command type
Memory Read (type 6). Note that during a non-burst
read operation, all byte lanes will always be active. The
Am79C978 controller will internally discard unneeded
bytes.
The Am79C978 controller typically performs more than
one non-burst read transaction within a single bus
mastership period. FRAME is dropped between con-
secutive non-burst read cycles. REQ stays asserted
until FRAME is asserted for the last transaction. The
Am79C978 controller supports zero wait state read cy-
cles. It asserts IRDY immediately after the address
phase and at the same time starts sampling DEVSEL.
Figure 14 shows two non-burst read transactions. The
first transaction has zero wait states. In the second
transaction, the target extends the cycle by asserting
TRDY one clock later.
Basic Burst Read Transfer
The Am79C978 controller supports burst mode for all
bus master read operations. The burst mode must be
enabled by setting BREADE (BCR18, bit 6). To allow
burst transfers in descriptor read operations, the
Am79C978 controller must also be programmed to use
SWSTYLE 3 (BCR20, bits 7-0). All burst read accesses
to the initialization block and descriptor ring are of the
PCI command type Memory Read (type 6). Burst read
accesses to the transmit buffer typically are longer than
two data phases. When MEMCMD (BCR18, bit 9) is
cleared to 0, all burst read accesses to the transmit
buffer are of the PCI command type Memory Read Line
(type 14). When MEMCMD (BCR18, bit 9) is set to 1,
all burst read accesses to the transmit buffer are of the
PCI command type Memory Read Multiple (type 12).
AD[1:0] will both be 0 during the address phase indicat-
ing a linear burst order. Note that during a burst read
operation, all byte lanes will always be active. The
Am79C978 controller will internally discard unneeded
bytes.
The Am79C978 controller will always perform only a
single burst read transaction per bus mastership pe-
riod, where
transaction
is defined as one address
phase and one or multiple data phases. The
Am79C978 controller supports zero wait state read cy-
cles. It asserts IRDY immediately after the address
phase and at the same time starts sampling DEVSEL.
FRAME is deasserted when the next to last data phase
is completed.
Figure 15 shows a typical burst read access. The
Am79C978 controller arbitrates for the bus, is granted
access, reads three 32-bit words (DWord) from the sys-
tem memory, and then releases the bus. In the exam-
ple, the memory system extends the data phase of
each access by one wait state. The example assumes
that EXTREQ (BCR18, bit 8) is cleared to 0, therefore,
REQ is deasserted in the same cycle as FRAME is as-
serted.
FRAME
CLK
AD
IRDY
C/
BE
REQ
GNT
1
2
3
4
5
CMD
ADDR
22206B-16
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C981 | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C981JC | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C982 | basic Integrated Multiport Repeater (bIMR) |
| AM79C982-4JC | basic Integrated Multiport Repeater (bIMR) |
| AM79C982-8JC | basic Integrated Multiport Repeater (bIMR) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C978A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978AKC\\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C978AKC\W | 制造商:Advanced Micro Devices 功能描述: |
| AM79C978AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。