
Am79C978
195
TBR16: 10BASE-T INTERRUPT Status and Enable
Register (Register 16)
The Interrupt bits indicate when there is a change in the
Link Status, Duplex Mode, Auto-Negotiation status, or
Speed status. Register 16 contains the interrupt status
and interrupt enable bits. The status is always updated
whether or not the interrupt enable bits are set. When
an interrupt occurs, the system will need to read the in-
terrupt register to clear the status bits and determine
the course of action needed. See Table 74.
Table 74.
TBR16: 10BASE-T INTERRUPT Status and Enable Register (Register 16)
Note:
1. All bits, except bit 13, are cleared on read (COR). The register must be read twice to see if it has been cleared.
Bit(s)
Name
Description
Read/
Write
H/W or Soft
Reset
15:14
Reserved
RO
0
13
Interrupt Test Enable
(Note 1)
1 = When this bit is set, setting bits 12:9 of this register
will cause a condition that will set bits 4:1
accordingly. The effect is to test the register bits with
a forced interrupt condition.
0 = Bits 4:1 are only set if the interrupt condition (if any
bits in 12:9 are set) occurs.
R/W
0
12
Link Status Change
Enable
1 = Link Status Change enable
0 = This interrupt is masked
R/W
0
11
Duplex Mode Change
Enable
1 = Duplex Mode Change enable
0 = This interrupt is masked
R/W
0
10
Auto-Neg Change
Enable
1 = Auto-Negotiation Change enable
0 = This interrupt is masked
R/W
0
9
Speed Change
Enable
1 = Speed Change enable
0 = This interrupt is masked
R/W
0
8
Global
Enable
1= Global Interrupt enable
0 = This interrupt is masked
R/W
0
7:5
Reserved
RO
0
4
Link Status Change
1 = Link Status has changed on a port
0 = No change in Link Status
RO,
LH
0
3
Duplex Mode Change
1 = Duplex Mode has changed on a port
0 = No change in Duplex mode
RO,
LH
0
2
Auto-Negotiation Change
1 = Auto-Neg status has changed on a port
0 = No change in Auto-Neg status
RO,
LH
0
1
Speed Change
1 = Speed status has changed on a port
0 = No change
RO,
LH
0
0
Global
1 = Indicates a change in status of any of the above
interrupts
0 = Indicates no change in Interrupt Status
RO,
LH
0