- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366551 > AM79C976KCW (ADVANCED MICRO DEVICES INC) PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller PDF資料下載
參數(shù)資料
| 型號： | AM79C976KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| 中文描述： | 1 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 71/309頁 |
| 文件大?。?/td> | 2070K |
| 代理商： | AM79C976KCW |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁當前第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁第245頁第246頁第247頁第248頁第249頁第250頁第251頁第252頁第253頁第254頁第255頁第256頁第257頁第258頁第259頁第260頁第261頁第262頁第263頁第264頁第265頁第266頁第267頁第268頁第269頁第270頁第271頁第272頁第273頁第274頁第275頁第276頁第277頁第278頁第279頁第280頁第281頁第282頁第283頁第284頁第285頁第286頁第287頁第288頁第289頁第290頁第291頁第292頁第293頁第294頁第295頁第296頁第297頁第298頁第299頁第300頁第301頁第302頁第303頁第304頁第305頁第306頁第307頁第308頁第309頁
8/01/00
Am79C976
71
P R E L I M I N A R Y
If REX_UFLO (CMD3, bit 7) is set, the transmitter will
not flush the frame data from the transmit FIFO after a
transmit FIFO underflow error occurs. Instead, it will
wait until the entire frame has been copied into the
transmit FIFO, and then it will restart the transmission
process.
(
The XmtLossCarrier counter is incremented if transmit
is attempted when the LINK_STAT bit in the STAT0 reg-
ister is 0.
(##
A late collision will be detected when the device is op-
erating in half-duplex mode and a collision condition
occurs after one slot time (512 bit times) after the trans-
mit process was initiated (first bit of preamble com-
menced). When it detects a late collision, the
Am79C976 controller will increment the XmtLateColli-
sion counter. If RTRY_LCOL (CMD3, bit 16) is cleared
to 0, the controller will abandon the transmit process for
that frame, and process the next transmit frame in the
ring. If the RTRY_LCOL bit is set to 1, transmission at-
tempts that incur late collisions will be retried up to a
maximum of 16 attempts.
* +#,
An underflow error occurs when the transmitter runs
out of data from the transmit FIFO in the middle of a
transmission. When this happens, an inverted FCS is
appended to the frame so that the intended receiver will
ignore the frame, and the XmtUnderrunPkts counter is
incremented. If REX_UFLO (CMD3, bit 17) is set to 1,
the transmitter will then wait until the entire frame has
been loaded into the transmit FIFO, and then it will re-
start the transmission of the same frame. If the
REX_UFLO is cleared to 0, the transmitter will not at-
tempt to retransmit the aborted frame.
Receive Operation
The receive operation and features of the Am79C976
controller are controlled by programmable options. The
Am79C976 controller uses a large receive FIFO to pro-
vide frame buffering for increased system latency, au-
tomatic flushing of collision fragments (runt packets),
automatic receive pad stripping, and a variety of ad-
dress match options.
((0!!
Automatic pad field stripping is enabled by setting the
ASTRP_RCV bit in CSR4. This can provide flexibility in
the reception of messages using the IEEE 802.3 frame
format.
The device can be programmed to accept all receive
frames regardless of destination address by setting the
PROM bit in CSR15. Acceptance of unicast and broad-
cast frames can be individually turned off by setting the
DRCVPA or DRCVBC bits in CSR15. The Physical Ad-
dress register (CSR12 to CSR14) stores the address
that the Am79C976 controller compares to the destina-
tion address of the incoming frame for a unicast ad-
dress match. The Logical Address Filter register
(CSR8 to CSR11) serves as a hash filter for multicast
address match.
The point at which the controller will start to transfer
data from the receive FIFO to buffer memory is con-
trolled by the RCVFW bits in CSR80. The default es-
tablished during H_RESET is 01b, which sets the
watermark flag at 64 bytes filled.
For test purposes, the Am79C976 controller can be
programmed to accept runt packets of 12 bytes or
larger by setting RPA in CSR124.
#(+
The Am79C976 controller supports three types of ad-
dress matching: unicast, multicast, and broadcast. The
normal address matching procedure can be modified
by programming three bits in CSR15, the mode register
(PROM, DRCVPA, and DRCVBC).
If the first bit received after the SFD (the least signifi-
cant bit of the first byte of the destination address field)
is 0, the frame is unicast, which indicates that the frame
is meant to be received by a single node. If the first bit
received is 1, the frame is multicast, which indicates
that the frame is meant to be received by a group of
nodes. If the destination address field contains all 1s,
the frame is broadcast, which is a special type of multi-
cast. Frames with the broadcast address in the destina-
tion address field are meant to be received by all nodes
on the local area network.
When a unicast frame arrives at the Am79C976 con-
troller, the controller will accept the frame if the destina-
tion address field of the incoming frame exactly
matches the 6-byte station address stored in the Phys-
ical Address registers (PADR, CSR12 to CSR14). The
byte ordering is such that the first byte received from
the network (after the SFD) must match the least signif-
icant byte of CSR12 (PADR[7:0]), and the sixth byte re-
ceived must match the most significant byte of CSR14
(PADR[47:40]).
When DRCVPA (CSR15, bit 13) is set to 1, the
Am79C976 controller will not accept unicast frames.
If the incoming frame is multicast, the Am79C976 con-
troller performs a calculation on the contents of the
destination address field to determine whether or not to
accept the frame. This calculation is explained in the
section that describes the Logical Address Filter
(LADRF).
When all bits of the LADRF registers are 0, no multicast
frames are accepted, except for broadcast frames.
相關PDF資料 |
PDF描述 |
|---|---|
| AM79C978AKCW | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978AVCW | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C978 | Single-Chip 1/10 Mbps PCI Home Networking Controller |
| AM79C981 | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
| AM79C981JC | Integrated Multiport Repeater Plus⑩ (IMR+⑩) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C976KD | 制造商:Advanced Micro Devices 功能描述:ETHERNET:MEDIA ACCESS CONTROLLER (MAC) |
| AM79C976KF | 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP 制造商:AMD (Advanced Micro Devices) 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP |
| AM79C976KI | 制造商:Advanced Micro Devices 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP 制造商:AMD (Advanced Micro Devices) 功能描述:Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 208-Pin PQFP |
| AM79C976KIW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PRO⑩ 10/100 Mbps PCI Ethernet Controller |
| AM79C978 | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Single-Chip 1/10 Mbps PCI Home Networking Controller |
發(fā)布緊急采購，3分鐘左右您將得到回復。