參數(shù)資料
型號(hào): AM79C971KCW
廠商: ADVANCED MICRO DEVICES INC
元件分類(lèi): 微控制器/微處理器
英文描述: IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C TSSOP-56 35/TUBE
中文描述: 4 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝: PLASTIC, QFP-160
文件頁(yè)數(shù): 26/265頁(yè)
文件大?。?/td> 3190K
代理商: AM79C971KCW
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26
Am79C971
RXCLK
Receive Clock
RXCLK is an input. The rising edges of the RXCLK sig-
nal are used to sample the data on the RXDAT input
whenever the RXEN input is HIGH.
Input
Note:
The RXCLK pin is multiplexed with the RX_CLK
pin.
When RST is active, RXCLK is an input for NAND tree
testing
.
RXDAT
Receive Data
RXDAT is an input. The rising edges of the RXCLK sig-
nal are used to sample the data on the RXDAT input
whenever the RXEN input is HIGH.
Input
Note:
The RXDAT pin is multiplexed with the RX_ER
pin.
When RST is active, RXDAT is an input for NAND tree
testing
.
RXEN
Receive Enable
RXEN is an input. When this signal is HIGH, it indicates
to the core logic that the data on the RXDAT input pin
is valid.
Input
Note:
The RXEN pin is multiplexed with the CRS pin.
When RST is active, RXEN is an input for NAND tree
testing
.
TXCLK
Transmit Clock
TXCLK is an input that provides a clock signal for MAC
activity, both transmit and receive. The rising edges of
the TXCLK can be used to validate TXDAT output data.
Input
Note:
The TXCLK pin is multiplexed with the TX_CLK
pin.
When RST is active, TXCLK is an input for NAND tree
testing
.
TXDAT
Transmit Data
TXDAT is an output that provides the serial bit stream
for transmission, including preamble, SFD, data, and
FCS field, if applicable.
Output
Note:
The TXDAT pin is multiplexed with the TXD[0]
pin.
When RST is active, TXDAT is an input for NAND tree
testing
.
TXEN
Transmit Enable
TXEN is an output that provides an enable signal for
transmission. Data on the TXDAT pin is not valid unless
the TXEN signal is HIGH.
Output
Note:
The TXEN pin is multiplexed with the TX_EN
pin.
When RST is active, TXEN is an input for NAND tree
testing
.
External Address Detection Interface
EAR
External Address Reject Low
The incoming frame will be checked against the inter-
nally active address detection mechanisms and the re-
sult of this check will be OR
d with the value on the EAR
pin. The EAR pin is defined as REJECT. The pin value
is OR
d with the internal address detection result to de-
termine if the current frame should be accepted or re-
jected.
Input
The EAR pin
must not
be left unconnected, it should
be tied to VDD through a resistor.
Note:
The EAR pin is multiplexed with the SLEEP pin.
When RST is active, EAR is an input for NAND tree
testing
.
SFBD
Start Frame-Byte Delimiter
For the Internal PHY during External Address
Detection:
Output
An initial rising edge on the SFBD signal indicates that
a start of frame delimiter has been detected. The serial
bit stream will follow on the SRD signal, commencing
with the destination address field. SFBD will go high for
4 bit times (400 ns when operating at 10 Mbps) after
detecting the second
1
in the SFD (Start of Frame De-
limiter) of a received frame. SFBD will subsequently
toggle every 4 bit times (1.25 MHz frequency when op-
erating at 10 Mbps) with each rising edge indicating the
first bit of each subsequent byte of the received serial
bit stream. See the
EADI Rejection Timing with Internal
PHY
timing diagram for details. SFBD will be active
only during frame reception.
For the External PHY attached to the Media Inde-
pendent Interface during External Address Detec-
tion:
An initial rising edge on the SFBD signal indicates that
a start of valid data is present on the RXD[3:0] pins.
SFBD will go high for one nibble time (400 ns when op-
erating at 10 Mbps and 40 ns when operating at 100
Mbps) one RX_CLK period after RX_DV has been as-
serted and RX_ER is deasserted and the detection of
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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AM79C972BKC\\W 制造商:Advanced Micro Devices 功能描述:
AM79C972BKC\W 制造商:Advanced Micro Devices 功能描述:
AM79C972BKCW 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support