- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄366550 > AM79C970AKC (ADVANCED MICRO DEVICES INC) PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C970AKC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP13 |
| 封裝： | CARRIER RING, PLASTIC, QFP-132 |
| 文件頁(yè)數(shù)： | 74/219頁(yè) |
| 文件大?。?/td> | 1065K |
| 代理商： | AM79C970AKC |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)當(dāng)前第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)
AMD
P R E L I M I N A R Y
74
Am79C970A
interFrame gap to be generated, leading to a potential
reception failure of a subsequent frame. To enhance
system robustness the following optional measures,as
specified in 4.2.8, are recommended when InterFrame
Spacing Part 1 is other than ZERO:
1. Upon completing a transmission, start timing the
interpacket gap, as soon as transmitting and carrier
Sense are both false.
2. When timing an interFrame gap following reception,
reset the interFrame gap timing if carrier Sense be-
comes true during the first 2/3 of the interFrame gap
timing interval. During the final 1/3 of the interval the
timer shall not be reset to ensure fair access to the
medium. An initial period shorter than 2/3 of the
interval is permissible including ZERO.”
The MAC engine implements the optional receive two
part deferral algorithm, with a first part inter-frame-
spacing time of 6.0
μ
s. The second part of the
inter-frame-spacing interval is therefore 3.6
μ
s.
The PCnet-PCI II controller will perform the two part de-
ferral algorithm as specified in Section 4.2.8 (Process
Deference). The Inter Packet Gap (IPG) timer will start
timing the 9.6
μ
s InterFrameSpacing after the receive
carrier is deasserted. During the first part deferral (Inter-
Frame Spacing Part1 – IFS1) the PCnet-PCI II control-
ler will defer any pending transmit frame and respond to
the receive message. The IPG counter will be cleared to
ZERO continuously until the carrier deasserts, at which
point the IPG counter will resume the 9.6
μ
s count once
again. Once the IFS1 period of 6.0
μ
s has elapsed, the
PCnet-PCI II controller will begin timing the second part
deferral (Inter-Frame Spacing Part2 – IFS2) of 3.6
μ
s.
Once IFS1 has completed, and IFS2 has commenced,
the PCnet-PCI II controller will not defer to a receive
frame if a transmit frame is pending. This means that the
PCnet-PCI II controller will not attempt to receive the re-
ceive frame, since it will start to transmit, and generate a
collision at 9.6
μ
s. The PCnet-PCI II controller will com-
plete the preamble (64-bit) and jam (32-bit) sequence
before ceasing transmission and invoking the random
backoff algorithm.
This transmit two part deferral algorithm is implemented
as an option which can be disabled using the DXMT2PD
bit in CSR3. Two part deferral after transmission is
useful for ensuring that severe IPG shrinkage cannot
occur in specific circumstances, causing a transmit
message to follow a receive message so closely as to
make them indistinguishable.
During the time period immediately after a transmission
has been completed, the external transceiver (in the
case of a standard AUI connected device), should
generate the SQE Test message (a nominal 10 MHz
burst of 5–15 Bit Times duration) on the CI
±
pair (within
0.6–1.6
μ
s after the transmission ceases). During the
time period in which the SQE Test message is expected
the PCnet-PCI II controller will not respond to receive
carrier sense.
See ANSI/IEEE Std 802.3-1990 Edition, 7.2.4.6 (1):
“At the conclusion of the output function, the DTE opens
a time window during which it expects to see the
signal_quality_error signal asserted on the Control
In circuit. The time window begins when the
CARRIER_STATUS becomes CARRIER_OFF. If exe-
cution of the output function does not cause
CARRIER_ON to occur, no SQE test occurs n the DTE.
The duration of the window shall be at east 4.0
μ
s but no
more than 8.0
μ
s. During the time window the Carrier
Sense Function is inhibited.”
The PCnet-PCI II controller implements a carrier sense
“blinding” period of 4.0
μ
s length starting from the
deassertion of carrier sense after transmission. This ef-
fectively means that when transmit two part deferral is
enabled (DXMT2PD is cleared) the IFS1 time is from
4
μ
s to 6
μ
s after a transmission. However, since IPG
shrinkage below 4
μ
s will rarely be encountered on a
correctly configured network, and since the fragment
size will be larger than the 4
μ
s blinding window, the IPG
counter will be reset by a worst case IPG shrinkage/frag-
ment scenario and the PCnet-PCI II controller will defer
its transmission. If carrier is detected within the 4.0 to
6.0
μ
s IFS1 period, the PCnet-PCI II controller will not
restart the “blinding” period, but only restart IFS1.
Collision Handling
Collision detection is performed and reported to
the MAC engine by the integrated Manchester
Encoder/Decoder (MENDEC).
If a collision is detected before the complete preamble/
SFD sequence has been transmitted, the MAC Engine
will complete the preamble/SFD before appending the
jam sequence. If a collision is detected after the pream-
ble/SFD has been completed, but prior to 512 bits being
transmitted, the MAC Engine will abort the transmis-
sion, and append the jam sequence immediately. The
jam sequence is a 32-bit all ZEROs pattern.
The MAC Engine will attempt to transmit a frame a total
of 16 times (initial attempt plus 15 retries) due to normal
collisions (those within the slot time). Detection of colli-
sion will cause the transmission to be re-scheduled to a
time determined by the random backoff algorithm. If a
single retry was required, the ONE bit will be set in the
transmit frame status. If more than one retry was re-
quired, the MORE bit will be set. If all 16 attempts experi-
enced collisions, the RTRY bit will be set (ONE and
MORE will be clear), and the transmit message will be
flushed from the FIFO. If retries have been disabled by
setting the DRTY bit in CSR15, the MAC Engine will
abandon transmission of the frame on detection of the
first collision. In this case, only the RTRY bit will be set
and the transmit message will be flushed from the FIFO.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C970A | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVCW | PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970 | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C971VCW | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| AM79C971 | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AKC\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM79C970AKCW | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AVC | 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AVC\\W | 制造商:Advanced Micro Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。