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參數(shù)資料
| 型號(hào)： | AM79C940VCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Media Access Controller for Ethernet (MACE) |
| 中文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP80 |
| 封裝： | TQFP-80 |
| 文件頁(yè)數(shù)： | 26/122頁(yè) |
| 文件大?。?/td> | 914K |
| 代理商： | AM79C940VCW |
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AMD
26
Am79C940
INTR
Interrupt (Output, Open Drain)
An attention signal indicating that one or more of the fol-
lowing status flags are set: XMTINT, RCVINT, MPCO,
RPCO, RCVCCO, CERR, BABL or JAB. Each interrupt
source can be individually masked. No interrupt condi-
tion can take place in the MACE device immediately af-
ter a hardware or software reset.
RESET
Reset (Input)
Reset clears the internal logic. Reset can be asynchro-
nous to SCLK, but must be asserted for a minimum
duration of 15 SCLK cycles.
SCLK
System Clock (Input)
The system clock input controls the operational fre-
quency of the slave interface to the MACE device and
the internal processing of frames. SCLK is unrelated to
the 20 MHz clock frequency required for the
802.3/Ethernet interface. The SCLK frequency range is
1 MHz–25 MHz.
EDSEL
System Clock Edge Select (Input)
EDSEL is a static input that allows System Clock
(SCLK) edge selection. If EDSEL is tied high, the bus in-
terface unit will assume falling edge timing. If EDSEL is
tied low, the bus interface unit will assume rising edge
timing, which will effectively invert the SCLK as it enters
the MACE device, i.e., the address, control lines (
CS
,
R/
W
,
FDS
, etc) and data are all latched on the rising
edge of SCLK, and data out is driven off the rising edge
of SCLK.
TC
Timing Control (Input)
The Timing Control input conditions the minimum num-
ber of System Clocks (SCLK) cycles taken to read or
write the internal registers and FIFOs.
TC
can be used
as a wait state generator, to allow additional time for
data to be presented by the host during a write cycle, or
allow additional time for the data to be latched during a
read cycle.
TC
has an internal (
SLEEP
disabled) pull up.
Timing Control
Number of
Clocks
TC
1
2
0
3
IEEE 1149.1 TEST ACCESS PORT (TAP)
INTERFACE
TCK
Test Clock (Input)
The clock input for the boundary scan test mode
operation. TCK can operate up to 10 MHz. TCK has an
internal (not
SLEEP
disabled) pull up.
TMS
Test Mode Select (Input)
A serial input bit stream used to define the specific
boundary scan test to be executed. TMS has an internal
(not
SLEEP
disabled) pull up.
TDI
Test Data Input (Input)
The test data input path to the MACE device. TDI has an
internal (not
SLEEP
disabled) pull up.
TDO
Test Data Out (Output)
The test data output path from the MACE device.
GENERAL INTERFACE
XTAL1
Crystal Connection (Input)
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. Internally, the
20 MHz crystal frequency is divided by two which deter-
mines the network data rate. Alternatively, an external
20 MHz CMOS-compatible clock signal can be used to
drive this pin. The MACE device supports the use of 50
pF crystals to generate a 20 MHz frequency which is
compatible with the IEEE 802.3 network frequency
tolerance and jitter specifications.
XTAL2
Crystal Connection (Output)
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. If an external
clock generator is used on XTAL1, then XTAL2 should
be left unconnected.
SLEEP
Sleep Mode (Input)
The optimal power savings made is extracted by assert-
ing the
SLEEP
pin with both the Auto Wake (AWAKE bit)
and Remote Wake (RWAKE bit) functions disabled. In
this “deep sleep” mode, all outputs will be forced into
their inactive or high impedance state, and all inputs will
be ignored except for the
SLEEP
,
RESET
, SCLK, TCK,
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