參數(shù)資料
型號(hào)： AM79C864AKC
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： Physical Layer Controller With Scrambler (PLC-S)
中文描述： 0 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP120
封裝： PLASTIC, QFP-120
文件頁(yè)數(shù)： 25/51頁(yè)
文件大?。?/td> 271K
代理商： AM79C864AKC
AMD
P R E L I M I N A R Y
3-27
Am79C864A
The value in the TNE Clock Divider is contained in bits 9
and 8 of the CLK_DIV at address 14 (hex).
The TNE Timer is used to time the length of (potential)
noise events while the PCM is in the ACTIVE state. The
TNE Timer is started whenever the Line State Machine
transitions from Idle Line State to Noise Line State, Ac-
tive Line State, or Unknown Line State. If the timer ex-
pires before the LSM recognizes Idle Line State again,
the PCM transitions to the BREAK state.
The timer is loaded with a two’s complement value and
counts up until it reaches zero. In normal operation the
timer is loaded by the PCM from the NS_MAX Timing
Parameter Register, which contains the two’s comple-
ment of the time value in 0.32
μ
s units, whenever the
LSM leaves Idle Line State. At the same time the TNE
Timer is loaded, the TNE Clock Divider is loaded
with zero.
When the PCM is in the MAINT state the TNE timer can
be loaded directly from the Node Processor. The Node
Processor accomplishes this by writing a 16-bit value
which is loaded into the timer (the TNE Clock Divider is
loaded with zero). The value written is the two’s comple-
ment of the time in 0.32
μ
s units. If the PCM is not in the
MAINT state when a write is attempted to the TNE timer,
the NP_ERR bit in the INTR_EVENT register will be set
and the timer will not be loaded.
Note that through use of the NOISE_TIMER bit in the
PLC_CNTRL_A register, the TNE Timer can be used to
time noise duration when the PCM is in the MAINT state
without the timer having to be explicitly loaded by the
Node Processor. The Node Processor should not at-
tempt to load the TNE Timer when the NOISE_TIMER
bit in the PLC_CNTRL_A is set. If this condition is vio-
lated the NP_ERR bit in the INTR_EVENT register will
be set and the timer will not be loaded.
The timer may also be used in 16-bit mode, where the
TNE Clock Divider is bypassed and the timer is incre-
mented every 80 ns when in operation. In this mode the
value loaded into the timer is the two’s complement of
the time remaining in 80 ns units. This feature, con-
trolled by the TNE_16BIT bit in the PLC_CNTRL_A reg-
ister, is intended for test purposes, where it is desirable
to run the timer for only short periods of time.
Physical Connection Management Timing
Parameters
The PCM uses a number of different timing parameters
while forming a physical connection. The parameters
are programmable and must be written by the node
processor. The registers are readable at any time. The
parameters are 16 bits in length and are loaded into the
TPC Timer. They hold the two’s complement of the time
in 20.48
μ
s (2
8
times 80 ns) units. They have a maximum
value of about 1.34 seconds (2
16
times 20.48
μ
s). When
the TPC Timer is in 16-bit mode the timing parameters
are the two’s complement of the time in 80 ns units and
can have a maximum value of about 5.24 ms (2
16
times
80 ns).
In addition to the TPC Timing Parameters, there is one
timing parameter used by the TNE Timer. Unlike the
TPC Timing Parameters, NS_MAX holds the two’s com-
plement of the time in 0.32
μ
s (2
2
times 80 ns) units. It
can have a maximum value of about 20.97 ms (2
16
times
0.32
μ
s). When the TNE Timer is in 16-bit mode,
NS_MAX is the two’s complement of the time in 80 ns
units and can have a maximum value of about 5.24 ms
(2
16
times 80 ns).
Table 7 summarizes the PCM timing parameters.
Minimum Connect State Time Register (C_Min)
The Minimum Connect State Time (C_Min) register has
address 06 (hex). It has a recommended value of 1.6 ms
(FFB2 hex in 2’s complement). This is the minimum time
required to remain in the Connect State to assure that
the other end has recognized HALT Line State.
Minimum Line State Transmit Time Register
(TL_Min)
The Minimum Line State Transmit Time Register
(TL_Min) has address 07 (hex). It has a recommended
value of 0.03 ms (FFFE hex in 2’s complement). This is
the minimum time required to transmit a Line State be-
fore advancing to the next PCM state.
Minimum Break Time Register (TB_MIN)
The Minimum Break Time (TB_MIN) register has ad-
dress 08 (hex). It has a recommended value of 5 ms
(FF10 hex in 2’s complement). When PCM performs a
break (in state BREAK), the break shall be of adequate
length to allow time for a response to be seen on the in-
bound physical link. This time allows for the possibility of
a bypass failure mode in this or a neighboring station
that could cause four PHYs to be connected in a loop
and produce an invalid response to the break. The mini-
mum break time guarantees that in this case the re-
sponse to the break will propagate around the loop and
be seen on the inbound link.
Signaling Timeout Register (T_OUT)
The Signaling Timeout (T_OUT) register has address
09 (hex). It has a recommended value of 100 ms (ECED
hex in 2’s complement). A response from a neighboring
PCM must be received by T_OUT. When a response is
expected and no transition is made in T_OUT time, a
transition is made to the BREAK state.
Link Confidence Test Time Register (LC_LENGTH)
The Link Confidence Test (LCT) Time register
(LC_LENGTH) has address 0B (hex). This register
specifies the time duration of the LCT and limits the du-
ration of loopback to prevent deadlock. It has a recom-
mended value of 50 ms (F676 hex in 2’s complement)
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