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| 型號： | AM79C864AKC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Physical Layer Controller With Scrambler (PLC-S) |
| 中文描述： | 0 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP120 |
| 封裝： | PLASTIC, QFP-120 |
| 文件頁數(shù)： | 17/51頁 |
| 文件大小： | 271K |
| 代理商： | AM79C864AKC |
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AMD
P R E L I M I N A R Y
3-19
Am79C864A
Table 2. PLC_CNTRL_A (continued)
Bit
Name
Definition
06
FOT_OFF
The setting of this bit will cause the assertion of the
FOTOFF
output pin of the PLC-S.
Read PLC_CNTRL_C register description for behavior of this signal when scrambling/
descrambling is enabled.
05
EB_LOC_LOOP
When EB_LOC_LOOP is set, a loopback path is set up in the PLC-S chip just prior to the
framer. Data from the PLC-S transit path are looped back to the input of the Framer. This
loopback path is also set up when the PLC-S is executing its Built In Self Test. Note that this
bit also controls which clock the Framer and Elasticity Buffer use. When it is not set, the
Recovered Byte Clock is derived from the RSCLK input pin, and when it is set, the BCLK is
used. Thus, when this bit gets set, a clock glitch could be created which could cause receive
data to be indeterminate for a clock cycle, spurious interrupts, and unknown values in the event
counters. EB_LOC_LOOP can only be written if the PCM is in the OFF or MAINT state.
04
LM_LOC_LOOP
When LM_LOC_LOOP is set a loopback path is set up in the PLC-S chip such that data
from TX 9–0 are passed through the PLC-S transmit path and looped back to the input
of the receive path just after the Elasticity Buffer at the LM Local Loopback MUX. This
loopback path differs from EB_LOC_LOOP in that the Framer and Elasticity Buffer are
bypassed. LM_LOC_LOOP can only be written if the PCM is in the OFF or MAINT
state.
03
SC_BYPASS
The SC_BYPASS bit provides limited control over the PLC-S’s data path by providing a
physical bypass of the PLC-S. If the PCM is in the MAINT state or if the CONFIG_CNTRL
bit in the PLC_CNTRL_B register is set, then the SC_BYPASS bit controls the Bypass
MUX. If both SC_BYPASS and REQ_ SCRUB are asserted then RX 9–0 is driven
with Idle symbols. If SC_BYPASS is asserted and REQ_SCRUB cleared, then
RX 9–0 is driven by the data entering the PLC-S at the TX 9–0 input. Otherwise,
RX 9–0 is driven by the data entering the PLC-S at the RDAT 4–0 input. This bit may be
written at any time, but only takes effect when the PCM is in its MAINT state or if the
CONFIG_CNTRL bit in the PLC_CNTRL_B register is set.
SC_BYPASS
SET
SET
RESET
RESET
When SC_REM_LOOP is set, a remote loopback path is set up inside the PLC-S where
symbols from the receive data path are looped back onto the transmit data path,
traversing all of both paths except for the receive data output latch and the transmit
data input latch. If the PCM is in the MAINT state or if the CONFIG_CNTRL bit in the
PLC_CNTRL_B register is set, then the SC_REM_LOOP bit controls the Remote
Loopback MUX. This loopback is used by the PCM to control the configuration and can
be used to monitor the ring or otherwise control configuration during normal operation.
This bit only has effect if the EB_LOC_LOOP, LM_LOC_LOOP and CIPHER_LPBCK
bits are not set. This bit may be written at any time, but only takes effect when the PCM is in
the MAINT state or if the CONFIG_CNTRL bit in the PLC_CNTRL_B register is set.
REQ_SCRUB
SET
RESET
RESET
SET
RX 9–0
IDLE
TX 9–0
RDAT 4–0
RDAT 4–0
02
SC_REM_LOOP
01
RF_DISABLE
When RF_DISABLE is set, it disables the Repeat Filter state machine in the PLC-S.
00
RUN_BIST
When RUN_BIST is set, it causes the PLC-S to begin running its Built In Self Test. The
completion of BIST is indicated via an interrupt. BIST can be stopped before
completion by clearing this bit. Once BIST has completed, this bit must be cleared and
set again before BIST will restart. For more detail, refer to pages 30
and 42 .
Reset PLC-S before setting this bit.
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