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| 型號： | AM79C864AKC |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Physical Layer Controller With Scrambler (PLC-S) |
| 中文描述： | 0 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP120 |
| 封裝： | PLASTIC, QFP-120 |
| 文件頁數(shù)： | 24/51頁 |
| 文件大小： | 271K |
| 代理商： | AM79C864AKC |
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AMD
P R E L I M I N A R Y
3-26
The SUPERNET 2 Family for FDDI 1994 Data Book
Table 6. PLC_STATUS_B (continued)
Bit
Name
Definition
06
PCM_SIGNALING
PCM_SIGNALING is a flag from the PCM indicating that the XMIT_VECTOR
register has been written. The XMIT_VECTOR and VECTOR_LENGTH registers
cannot be written when this flag is set.
05
LSF
The Line State Flag is used by the PCM to indicate that a given line state has been
received since entering the current state. It is cleared on every change of PCM state.
04
RCF
The Receive Code Flag is used by the PCM to indicate that the Receive Pseudo Code
has started execution. This flag is used to prevent the Receive Pseudo Code from
being started multiple times while in the NEXT state.
03
TCF
The Transmit Code Flag is used by the PCM to indicate that the Transmit Pseudo
Code has started execution. This flag is used to prevent the Transmit Pseudo Code
from being started multiple times while in the NEXT state.
02–00
BREAK_REASON
This field indicates the reason for the PCM state machine’s last transition to the
BREAK state. It is defined as follows:
BREAK_REASON
000
001
010
011
100
101
110
111
Description
The PCM state machine has not gone to the BREAK state.
PC_Start issued
TPC Timer expired after T_OUT
TNE Timer expired after NS_MAX
Quiet Line State detected
Idle Line State detected
Halt Line State detected
Reserved
Physical Connection Management (PCM) Timers
The PCM contains two timers, TPC and TNE. Both tim-
ers have a clock divider circuit to reduce the frequency
at which they are clocked.
TPC Timer
The TPC Timer is a 16-bit timer. In normal operation it is
read-only by the Node Processor. TPC is read at
address 12 (hex). When the PCM is in the MAINT state a
value can be written to TPC by writing TPC_LOAD_
VALUE at address 0E. The TPC Timer is incremented
by the output of an 8-bit clock divider circuit. It is incre-
mented every 20.48
μ
s (2
8
times 80 ns). The value in the
TPC Clock Divider is contained in bits 7 through 0 of the
CLK_DIV register at address 14 (hex).
The TPC Timer is used while the PCM is attempting to
establish a physical connection with a neighboring
PCM. It is used to ensure that state transitions proceed
at the desired rate.
The timer is loaded with a two’s complement value and
counts up until it reaches zero. In normal operation the
timer is loaded by the PCM from the TPC Timing
Parameter Registers, which contain the two’s comple-
ment of the time value in 20.48
μ
s units. At the same
time the TPC Timer is loaded, the TPC Clock Divider is
loaded with zero.
When the PCM is in the MAINT state, the TPC Timer can
be loaded directly from the Node Processor. The Node
Processor accomplishes this by writing a 16-bit value
which is loaded into the timer (the TPC Clock Divider is
loaded with zero). The value written is the two’s comple-
ment of the time in 20.48
μ
s units. If the PCM is not in the
MAINT state when a write is attempted to the TPC timer,
the NP_ERR bit in the INTR_EVENT register will be set
and the timer will not be loaded.
The timer may also be used in 16-bit mode, where the
TPC Clock Divider is bypassed and the timer is incre-
mented every 80 ns when in operation. In this mode the
value loaded into the timer is the two’s complement of
the time remaining in 80 ns units. This feature, con-
trolled by the TPC_16BIT bit in the PLC_CNTRL_A reg-
ister, is intended for test purposes, where it is desirable
to run the timer for only short periods of time.
TNE Timer
The TNE Timer is a 16-bit timer. In normal operation it is
read-only by the Node Processor. TNE is read at ad-
dress 13 (hex). When the PCM is in the MAINT state
and the NOISE_TIMER bit in the PLC_CNTRL_A regis-
ter is not set, a value can be written to TNE by writing
TNE_LOAD_VALUE at address 0F. The TNE Timer is
incremented by the output of a 2-bit clock divider circuit.
It is incremented every 0.32
μ
s (2
2
times 80 ns).
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