參數(shù)資料
型號: AM7969-125VBXA
廠商: Advanced Micro Devices, Inc.
英文描述: TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface)
中文描述: TAXIchip集成電路(透明異步Xmitter,接收器接口)
文件頁數(shù): 93/127頁
文件大?。?/td> 730K
代理商: AM7969-125VBXA
AMD
89
TAXIchip Integrated Circuits Technical Manual
8.2 Rec eiver Connec tions
Refer to Figure 8-2.
Grounding SERIN– puts the Receiver in Test Mode. SERIN+ is a single ended 100K
ECL NRZ input.
The X1 pin now becomes the bit rate clock input (bitclk), just like the CLK pin on the
Transmitter.
The CLK pin remains a byterate CLK out.
8.3 T iming Relationships in T est Mode
The timing parameters in Test Mode are similar to the parameters in standard mode.
Propagation delay values remain the same, however bit time relationships are now
calculated with respect to the new bit times. For example, using a bitclk = 1.0 kHz, which
is a 1 ms period, the byte time t
35
= 10 bits x 1 ms = 10 ms. In the same way t
37
, which is
the CLK falling to STRB rising delay is now [2 (t
35
/n) + 15 ns] = 2.015 ms. Note that
Setup and Hold times for SERIN to X1 are not specified and must be determined for
each application.
Figure 8-2
Rec eiver T est Mode Connec tions
DSTRB
DATA OUT
8, 9, 10
COMMAND OUT
4, 3, 2
VLTN
SERIN+
X2
RESET
CLK
DMS
Clock Recovery
Circuit
Digital or Analog
PLL
Am7969
Normal
Function
CNB
DMS Can Be
Set For 8, 9, or
10-Bit Mode
Normal
Function
X1
SERIN–
IGM
CMD STROBE
DATA STROBE
Single Ended
Input From
Transmitter
Byte Rate CLK Out
CSTRB
12330E-36
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