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參數(shù)資料
| 型號(hào)： | Am7968-175DMC |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| 中文描述： | TAXIchip集成電路（透明異步Xmitter，接收器接口） |
| 文件頁(yè)數(shù)： | 107/127頁(yè) |
| 文件大小： | 730K |
| 代理商： | AM7968-175DMC |
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AMD
103
TAXIchip Integrated Circuits Technical Manual
TAXI T
echnical
I
nformation
P
ublication
#89-10
S ubjec t: T AX I Rec eiver CS T RB and DS T RB Pulse Width
Question:
What is the maximum CSTRB and DSTRB pulse width
Answer:
The internal logic of the TAXI Receiver determines the pulse width of CSTRB and
DSTRB based on the timing of an internal clock (Bit Clock). Under normal conditions,
the pulse width will be 4-bit times wide in the 8-bit mode, and 5-bit times wide in the
9- and 10-bit modes. An exception to this typical width is upon re-sync which can cause
the pulse to be expanded by up to 5 bit times as the byte boundaries are re-aligned to
the incoming data stream.
The number of bit times used to represent data differs based on the operational mode;
in 8-bit mode, data is encoded into 10 bits, in 9-bit mode 11-bits, and in 10-bit mode
2 bits. For example, a Receiver operating with a 12.5 MHz crystal and utilizing 8-bit
mode will have a clock period of 80 ns (1/12.5 MHz = 80 ns). Internally the Receiver
divides this period by 10, forming the internal bit boundaries used to represent the
encoded data. This example yields a 8 ns (80 ns/10 = 8 ns) bit period, which translates
to a internal clock rate of 125 MHz (1/8 ns = 125 MHz). Figure 11. shows a timing
diagram of a TAXI Receiver internal clock and its relationship to CLK, Data, and Strobe
outputs. The Receiver utilizes this divided clock to define its internal logic states.
The CSTRB and DSTRB signals are generated by using these logic states and have a
fixed relationship to the incoming encoded data. The figure shows that from the
beginning of the byte (state 0), the CSTRB or DSTRB delay is two internal clock periods
before going high, and the signal remains high for four internal clock periods then
returns to a low logic level. Actual pulse width will vary from this ideal width due to signal
rise and fall delay, propagation delay and effects of loads external to the Receiver. The
data sheet parameters reflect these delays and normal manufacturing guard bands.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Am7968-175LMC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7969 | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7968-125DKC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7969-125DKC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| Am7968-175DKC | TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM7968-175JC | 制造商:Rochester Electronics LLC 功能描述: |
| AM7968-175JC-G | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AM7968-175LKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7968-175LMC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface) |
| AM7968-175PC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Transmitter |
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