參數(shù)資料
型號(hào)： AM29N323DT11AWKI
廠(chǎng)商： Advanced Micro Devices, Inc.
英文描述： 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
中文描述： 32兆位（2米× 16位）的CMOS 1.8伏，只有同時(shí)讀/寫(xiě)，突發(fā)模式閃存
文件頁(yè)數(shù)： 4/48頁(yè)
文件大小： 824K
代理商： AM29N323DT11AWKI
August 8, 2002
Am29N323D
3
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram of
Simultaneous Operation Circuit. . . . . . . . . . . . . . 5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .6
Special Handling Instructions for FBGA Package ....................6
Input/Output Descriptions . . . . . . . . . . . . . . . . . . .7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . .9
Table 1. Device Bus Operations ......................................................9
Requirements for Asynchronous ReadOperation(Non-Burst) 9
Requirements for Synchronous (Burst) ReadOperation ..........9
Programmable Wait State ......................................................10
Power Saving Function ...........................................................10
Simultaneous Read/Write Operations with ZeroLatency .......10
Writing Commands/Command Sequences ............................10
Accelerated ProgramOperation .............................................11
Autoselect Functions ..............................................................11
Automatic Sleep Mode ...........................................................11
RESET# Hardware Reset Input .............................................11
Output Disable Mode ..............................................................11
Hardware Data Protection ......................................................11
Low VCC Write Inhibit ............................................................12
Write Pulse “Glitch” Protection ...............................................12
Logical Inhibit ..........................................................................12
Table 2. Sector Address Table ........................................................13
Command Definitions . . . . . . . . . . . . . . . . . . . . . .15
Reading Array Data ................................................................15
Set Wait State Command Sequence ......................................15
Table 3. Third Cycle Address/Data .................................................15
Enable PS (Power Saving) Mode CommandSequence ........15
Sector Lock/Unlock Command Sequence ..............................15
Reset Command .....................................................................15
Autoselect Command Sequence ............................................16
ProgramCommand Sequence ...............................................16
Unlock Bypass Command Sequence .....................................16
Figure 1. ProgramOperation.......................................................... 17
Chip Erase Command Sequence ...........................................18
Sector Erase Command Sequence ........................................18
Erase Suspend/Erase Resume Commands ...........................19
Figure 2. Erase Operation............................................................... 19
Table 4. Command Definitions .......................................................20
Write Operation Status . . . . . . . . . . . . . . . . . . . . .21
DQ7: Data#Polling .................................................................21
Figure 3. Data#Polling Algorithm................................................... 21
DQ6: Toggle Bit I ....................................................................22
Figure 4. Toggle Bit Algorithm........................................................ 22
DQ2: Toggle Bit II ...................................................................23
Table 5. DQ6 and DQ2 Indications ................................................23
Reading Toggle Bits DQ6/DQ2 ...............................................23
DQ5: Exceeded Timng Limts ................................................23
DQ3: Sector Erase Timer .......................................................24
Table 6. Write Operation Status .....................................................24
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 25
Figure 5. MaximumNegative OvershootWaveform...................... 25
Figure 6. MaximumPositive OvershootWaveform........................ 25
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 25
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 7. Test Setup....................................................................... 27
Table 7. Test Specifications ...........................................................27
Key to Switching Waveforms. . . . . . . . . . . . . . . . 27
Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . 27
Figure 8. Input Waveforms and Measurement Levels................... 27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
Synchronous/Burst Read ........................................................28
Figure 9. Burst Mode Read............................................................ 28
Asynchronous Read ...............................................................29
Figure 10. Asynchronous Mode Read............................................ 29
Figure 11. Reset Timngs............................................................... 30
Erase/ProgramOperations .....................................................31
Figure 12. ProgramOperation Timngs.......................................... 32
Figure 13. Chip/Sector Erase Operations...................................... 33
Figure 14. Accelerated Unlock Bypass ProgrammngTimng........ 34
Figure 15. Data#Polling Timngs (DuringEmbeddedAlgorithm.. 35
Figure 16. Toggle Bit Timngs (DuringEmbeddedAlgorithm........ 35
Figure 17. Latency with Boundary Crossing.................................. 36
Figure 18. Initial Access with Power Saving (PS)
FunctionandAddressBoundaryLatency...................................... 37
Figure 19. Initial AccesswithAddressBoundaryLatency............. 38
Figure 20. Example of Five Wait States Insertion.......................... 39
Figure 21. Back-to-Back Read/Write Cycle Timngs...................... 40
Erase and Programming Performance . . . . . . . 41
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 42
FDD047—47-Pin Fine-Pitch Ball Grid Array
(FBGA)7x10mmpackage ...................................................42
Mask Set Revision . . . . . . . . . . . . . . . . . . . . . . . . 44
Appendix A: Daisy Chain Information . . . . . . . . 45
Table 8. Daisy Chain Part for 32Mbit 0.23 μmFlash Products
(FDD047, 7 x 10 mm .....................................................................45
Table 9. FDD047 Package Information ..........................................45
Table 10. FDD047 Connections .....................................................45
Figure 1. FDD047 Daisy Chain Layout
(TopView, BallsFacingDown)...................................................... 45
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 46
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