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| 型號： | AM29N323DT11AWKI |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 32兆位（2米× 16位）的CMOS 1.8伏，只有同時讀/寫，突發(fā)模式閃存 |
| 文件頁數(shù)： | 10/48頁 |
| 文件大?。?/td> | 824K |
| 代理商： | AM29N323DT11AWKI |
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August 8, 2002
Am29N323D
9
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device.
Table 1
lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Device Bus Operations
Legend:
L = Logic 0, H = Logic 1, X = Don’t Care.
Requirements for Asynchronous
Read Operation (Non-Burst)
To read data from the memory array, the system must
first assert a valid address on A/DQ0–A/DQ15 and
A16–A20, while driving AVD# and CE# to V
IL
. WE#
should remain at V
IH
. Note that CLK must remain low
for asynchronous read operations. The rising edge of
AVD# latches the address, after which the system can
drive OE# to V
IL
. The data will appear on
A/DQ0–A/DQ15. Since the memory array is divided
into two banks, each bank remains enabled for read
access until the command register contents are
altered.
Address access time (t
ACC
) is equal to the delay from
stable addresses to valid output data. The chip enable
access time (t
CE
) is the delay from the stable
addresses and stable CE# to valid data at the outputs.
The output enable access time (t
OE
) is the delay from
the falling edge of OE# to valid data at the output.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition.
Requirements for Synchronous (Burst)
Read Operation
The device is capable of continuous, sequential (linear)
burst operation. However, when the device first powers
up, it is enabled for asynchronous read operation. The
device will automatically be enabled for burst mode on
the first rising edge on the CLK input, while AVD# is
held low for one clock cycle. Prior to activating the clock
signal, the system should determine how many wait
states are desired for the initial word (t
IACC
) of each
burst session. The system would then write the Set
Wait Count command sequence (see
“Programmable
Wait State”
). The system may optionally activate the
PS mode (see
“Power Saving Function”
) by writing the
Enable PS Mode command sequence at this time, but
note that the PS mode can only be disabled by a hard-
ware reset. (See
“Command Definitions”
for further
details).
The initial word is output t
IACC
after the rising edge of
the first CLK cycle. Subsequent words are output t
BACC
Operation
CE#
OE#
WE#
A16–20
A/DQ0–15
RESET#
CLK
AVD#
Asynchronous Read
L
L
H
Addr In
I/O
H
L
Write
L
H
L
Addr In
I/O
H
L
Standby (CE#)
H
X
X
HIGH Z
HIGH Z
H
X
X
Hardware Reset
X
X
X
HIGH Z
HIGH Z
L
X
X
Burst Read Operations
Load Starting Burst Address
L
H
H
Addr In
I/O
H
Advance Burst to next address with appropriate
Data presented on the Data Bus
L
L
H
HIGH Z
Burst
Data Out
H
H
Terminate current Burst read cycle
H
X
H
HIGH Z
HIGH Z
H
X
Terminate current Burst read cycle via RESET#
X
X
H
HIGH Z
HIGH Z
L
X
X
Terminate current Burst read cycle and start new
Burst read cycle
L
H
H
HIGH Z
I/O
H
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