參數(shù)資料
型號： AM29LV800DB-120WCC
廠商： Advanced Micro Devices, Inc.
英文描述： Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 180pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Solder Coated (Sn/Pb, 70/30); Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: R Failure Rate
中文描述： 8兆位（1 M中的x 8-Bit/512畝x 16位），3.0伏的CMOS只引導(dǎo)扇區(qū)閃存
文件頁數(shù)： 25/51頁
文件大?。?/td> 1628K
代理商： AM29LV800DB-120WCC
January 21, 2005 Am29LV800D_00_A4_E
Am29LV800D
23
P R E L I M I N A R Y
prior to this, the device outputs the “comple-
ment,” or “0.” The system must provide an
address within any of the sectors selected for
erasure to read valid status information on DQ7.
After an erase command sequence is written, if
all sectors selected for erasing are protected,
Data# Polling on DQ7 is active for approxi-
mately 100 μs, then the device returns to
reading array data. If not all selected sectors are
protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the
selected sectors that are protected.
When the system detects DQ7 has changed
from the complement to true data, it can read
valid data at DQ7–DQ0 on the
following
read
cycles. This is because DQ7 may change asyn-
chronously with DQ0–DQ6 while Output Enable
(OE#) is asserted low. Figure 1, Data# Polling
Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.
Table 6 shows the outputs for Data# Polling on
DQ7. Figure 1 shows the Data# Polling algo-
rithm.
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output
pin that indicates whether an Embedded Algo-
rithm is in progress or complete. The RY/BY#
status is valid after the rising edge of the final
WE# pulse in the command sequence. Since
RY/BY# is an open-drain output, several
DQ7 = Data
Yes
No
No
DQ5 = 1
No
Yes
Yes
FAIL
PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data
START
Notes:
1. VA = Valid address for programming. During a
sector erase operation, a valid address is an
address within any sector selected for erasure.
During chip erase, a valid address is any
non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” be-
cause DQ7 may change simultaneously with DQ5.
Figure 1. Data# Polling Algorithm
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AM29LV800DT-120ED Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 1800pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-10%; Dielectric: Multilayer Ceramic; Temperature Coefficient: X7R (BX); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: 100% Tin (Sn); Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: P Failure Rate
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