參數(shù)資料
型號： AM29LV800DB-120WCC
廠商： Advanced Micro Devices, Inc.
英文描述： Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 180pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-5%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 0805; Termination: Solder Coated (Sn/Pb, 70/30); Body Dimensions: 0.080" x 0.050" x 0.055"; Container: Bag; Features: MIL-PRF-55681: R Failure Rate
中文描述： 8兆位（1 M中的x 8-Bit/512畝x 16位），3.0伏的CMOS只引導(dǎo)扇區(qū)閃存
文件頁數(shù)： 21/51頁
文件大?。?/td> 1628K
代理商： AM29LV800DB-120WCC
January 21, 2005 Am29LV800D_00_A4_E
Am29LV800D
19
P R E L I M I N A R Y
Note:
See Table 5 for program command sequence.
Figure 1. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip
erase command sequence is initiated by writing
two unlock cycles, followed by a set-up com-
mand. Two additional unlock write cycles are
then followed by the chip erase command,
which in turn invokes the Embedded Erase algo-
rithm. The device does
not
require the system
to preprogram prior to erase. The Embedded
Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data
pattern prior to electrical erase. The system is
not required to provide any controls or timings
during these operations. Table 5 shows the
address and data requirements for the chip
erase command sequence.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. Note
that a
hardware reset
during the chip erase
operation immediately terminates the opera-
tion. The Chip Erase command sequence should
be reinitiated once the device has returned to
reading array data, to ensure data integrity.
The system can determine the status of the
erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. See “Write Operation Status” for infor-
mation on these status bits. When the
Embedded Erase algorithm is complete, the
device returns to reading array data and
addresses are no longer latched.
Figure 1 illustrates the algorithm for the erase
operation. See the Erase/Program Operations
tables in “AC Characteristics” for parameters,
and to Figure 1 for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The
sector erase command sequence is initiated by
writing two unlock cycles, followed by a set-up
command. Two additional unlock write cycles
are then followed by the address of the sector to
be erased, and the sector erase command. Table
5 shows the address and data requirements for
the sector erase command sequence.
The device does
not
require the system to pre-
program the memory prior to erase. The
Embedded Erase algorithm automatically pro-
grams and verifies the sector for an all zero data
pattern prior to electrical erase. The system is
not required to provide any controls or timings
during these operations.
After the command sequence is written, a sector
erase time-out of 50 μs begins. During the time-
out period, additional sector addresses and
sector erase commands may be written.
Loading the sector erase buffer may be done in
any sequence, and the number of sectors may
be from one sector to all sectors. The time
between these additional cycles must be less
than 50 μs, otherwise the last address and
command might not be accepted, and erasure
may begin. It is recommended that processor
interrupts be disabled during this time to ensure
all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase
command is written. If the time between addi-
tional sector erase commands can be assumed
to be less than 50 μs, the system need not
monitor DQ3.
Any command other than
Sector Erase or Erase Suspend during the
time-out period resets the device to
reading array data.
The system must rewrite
the command sequence and any additional
sector addresses and commands.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
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