- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366412 > Am29F004B-B-70JE (Advanced Micro Devices, Inc.) 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory PDF資料下載
參數(shù)資料
| 型號： | Am29F004B-B-70JE |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| 中文描述： | 4兆位（512畝× 8位）的CMOS 5.0伏，只引導扇區(qū)閃存 |
| 文件頁數(shù)： | 15/37頁 |
| 文件大小： | 993K |
| 代理商： | AM29F004B-B-70JE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁
8/5/05
Am29F004B
13
A D V A N C E I N F O R M A T I O N
Hardware Data Protection
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might oth-
erwise be caused by spurious system level signals during
V
CC
power-up and power-down transitions, or from system
noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not accept any
write cycles. This protects data during V
CC
power-up and
power-down. The command register and all internal pro-
gram/erase circuits are disabled, and the device resets.
Subsequent writes are ignored until V
CC
is greater than V
LKO
.
The system must provide the proper signals to the control
pins to prevent unintentional writes when V
CC
is greater than
V
LKO
.
Write Pulse
Glitch
Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE#
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
IL
,
CE# = V
IH
or WE# = V
IH
. To initiate a write cycle, CE# and
WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up, the
device does not accept commands on the rising edge of
WE#. The internal state machine is automatically reset to
reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or sequences
into the command register initiates device operations. The
Command Definitions table defines the valid register
command sequences. Writing
incorrect
address and data
values
or writing them in the
improper sequence
resets the
device to reading array data.
All addresses are latched on the falling edge of WE# or CE#,
whichever happens later. All data is latched on the rising edge
of WE# or CE#, whichever happens first. Refer to the appro-
priate timing diagrams in
AC Characteristics on page 24
.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve data.
The device is also ready to read array data after completing
an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the
device enters the Erase Suspend mode. The system can
read array data using the standard read timings, except that
if it reads at an address within erase-suspended sectors, the
device outputs status data. After completing a programming
operation in the Erase Suspend mode, the system may once
again read array data with the same exception. See
Reset
Command
for more information on this mode.
The system
must
issue the reset command to re-enable the
device for reading array data if DQ5 goes high, or while in the
autoselect mode. See the
Reset Command
section, next.
See also “Requirements for Reading Array Data” in the
Device Bus Operations on page 8
section for more informa-
tion. The Read Operations table provides the read
parameters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the device resets the device to
reading array data. Address bits are don’t care for this
command.
The reset command may be written between the sequence
cycles in an erase command sequence before erasing
begins. This resets the device to reading array data. Once
erasure begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before programming
begins. This resets the device to reading array data (also
applies to programming in Erase Suspend mode). Once pro-
gramming begins, however, the device ignores reset
commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command
must
be written to
return to reading array data (also applies to autoselect during
Erase Suspend).
If DQ5 goes high during a program or erase operation, writing
the reset command returns the device to reading array data
(also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system
to access the manufacturer and devices codes, and deter-
mine whether or not a sector is protected. The Command
Definitions table shows the address and data requirements.
This method is an alternative to that shown in the Autoselect
Codes (High Voltage Method) table, which is intended for
PROM programmers and requires V
ID
on address bit A9.
The autoselect command sequence is initiated by writing two
unlock cycles, followed by the autoselect command. The
device then enters the autoselect mode, and the system may
read at any address any number of times, without initiating
another command sequence.
A read cycle at address XX00h or retrieves the manufacturer
code. A read cycle at address XX01h returns the device code.
A read cycle containing a sector address (SA) and the
address 02h in returns 01h if that sector is protected, or 00h
if it is unprotected. Refer to the Sector Address tables for valid
sector addresses.
The system must write the reset command to exit the autose-
lect mode and return to reading array data.
Byte Program Command Sequence
Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock write
相關PDF資料 |
PDF描述 |
|---|---|
| Am29F004B-B-70JF | 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| Am29F004B-B-70JI | 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| Am29F004B-T-70JE | 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| Am29F004B-T-70JF | 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
| Am29F004B-B-70JK | 4 Megabit (512 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AM29F010 | 制造商:Panasonic Industrial Company 功能描述:IC |
| AM29F010-120DGC1 | 制造商:Spansion 功能描述:1M FLASH KNOWN GOOD DIE (COMMERCIAL TEMP) - Gel-pak, waffle pack, wafer, diced wafer on film |
| AM29F010-120DGE1 | 制造商:Spansion 功能描述:1M FLASH KNOWN GOOD DIE (EXTEND TEMP) - Gel-pak, waffle pack, wafer, diced wafer on film |
| AM29F010-120DGI1 | 制造商:Spansion 功能描述:1M FLASH KNOWN GOOD DIE (INDUSTRIAL TEMP) - Gel-pak, waffle pack, wafer, diced wafer on film |
| AM29F010-120JC | 制造商:Advanced Micro Devices 功能描述: 制造商:Advanced Micro Devices 功能描述:NOR Flash, 128K x 8, 32 Pin, Plastic, PLCC 制造商:Analog Devices 功能描述:NOR Flash, 128K x 8, 32 Pin, Plastic, PLCC |
發(fā)布緊急采購，3分鐘左右您將得到回復。