參數(shù)資料
型號: AM29DS323DT50WMIN
廠商: Advanced Micro Devices, Inc.
英文描述: 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation Flash Memory
中文描述: 32兆位(4個M × 8位/ 2米x 16位),1.8伏的CMOS只,同時作業(yè)快閃記憶體
文件頁數(shù): 46/56頁
文件大?。?/td> 641K
代理商: AM29DS323DT50WMIN
44
Am29DS323D
23480A5 October10,2006
D A T A S H E E T
AC CHARACTERISTICS
Data Polling and Toggle Bit
Notes:
1. Not 100% tested.
See Figure 11 and
Table 16
for test specifications.
Parameter
Description
Test Setup
All Speed
Options
JEDEC
Std
Unit
t
AVAV
t
RC
Read Cycle Time
(Note 1)
Min
200
ns
t
AVQV
t
ACC
Address to Output Delay
CE#, OE# = V
IL
Max
200
ns
t
ELQV
t
CE
Chip Enable to Output Delay
OE# = V
IL
Max
200
ns
t
GLQV
t
OE
Output Enable to Output Delay
Max
50
ns
t
EHQZ
t
DF
Chip Enable to Output High Z
(Note 1)
Max
16
ns
t
GHQZ
t
DF
Output Enable to Output High Z
(Note 1)
Max
16
ns
t
AXQX
t
OH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
Min
0
ns
t
OEH
Output Enable Hold
Time
(Note 1)
Data Polling
and Toggle Bit
Min
10
ns
WE#
CE#
OE#
High Z
t
OE
High Z
DQ7
DQ0–DQ6
RY/BY#
t
BUSY
Complement
True
Addresses
VA
t
OEH
t
CE
t
CH
t
OH
t
DF
VA
VA
Status Data
Complement
Status Data
True
Valid Data
Valid Data
t
ACC
t
RC
Note:
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 21.
Data# Polling Timings (During Embedded Algorithms)
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