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| 型號： | AM29BDS643DT9BWLI |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | PROM |
| 英文描述： | 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 13.5 ns, PBGA48 |
| 封裝： | 11 X 10 MM, 0.50 MM PITCH, FBGA-48 |
| 文件頁數(shù)： | 46/46頁 |
| 文件大?。?/td> | 693K |
| 代理商： | AM29BDS643DT9BWLI |
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46
Am29BDS643D
P R E L I M I N A R Y
REVISION SUMMARY
Revision A (June 20, 2000)
initial release.
Revision A+1 (November 27, 2000)
Global
Deleted all references to non-handshaking option.
Ordering Information
Added “H’ designator to device package marking.
Requirements for Synchronous (Burst)
Read Operation
Changed the latency for address boundary crossing to
two cycles for all speeds of operation.
Autoselect Command Sequence
Corrected autoselect data for handshaking to 0041h.
Added table to section for feature clarification.
Chip Erase Command Sequence
Corrected the command sequence length during
unlock bypass mode from four cycles to two.
DC Characteristics table
Added specification for active burst mode current with
OE# high, I
CCB2
. Original I
CCB
specification is now
named I
CCB1
.
Program Command Sequence, Accelerated
Program Operation
Added text indicating that sectors must be unlocked
prior to raising V
PP
to V
ID
.
Table 4, Command Definitions
Corrected autoselect data for handshaking to 0041h.
AC Characteristics
I
Burst Mode Read figures (40 and 54 MHz):
Cor-
rected RDY waveform
to indicate behavior when PS
is enabled
and when RDY is in the high-impedence
stage
.
Accelerated Unlock Bypass Programming Timing
figure:
Modified Note 3 to indicate that sectors must be
unlocked prior to raising V
PP
to V
ID
.
Latency with Boundary Crossing (40 MHz) figure:
Deleted figure; all speed options have a two-cycle
latency.
Initial Access with Power Saving (PS) and Address
Boundary Latency figure
: Modified to show that
two-cycle latency is present, and that RDY is high for a
portion of the boundary latency.
Revision A+2 (November 30, 2000)
Figure 11, Asynchronous Mode Read
Corrected endpoint for t
AAVDS
specification.
Figure 17, Toggle Bit Timings
(During Embedded Algorithm)
Corrected OE# waveform during second VA (valid
address) period.
Revision A+3 (December 21, 2000)
Figure 9, Burst Mode Read (54 MHz) and Figure 10,
Burst Mode Read (40 MHz)
Corrected RDY waveform.
Trademarks
Copyright 2000 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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