參數(shù)資料
型號(hào)： AM29BDS643DT9BWLI
廠商： ADVANCED MICRO DEVICES INC
元件分類： PROM
英文描述： 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
中文描述： 4M X 16 FLASH 1.8V PROM, 13.5 ns, PBGA48
封裝： 11 X 10 MM, 0.50 MM PITCH, FBGA-48
文件頁(yè)數(shù)： 12/46頁(yè)
文件大?。?/td> 693K
代理商： AM29BDS643DT9BWLI
12
Am29BDS643D
P R E L I M I N A R Y
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 4 for com-
mand definitions).
The device offers three types of data protection at the
sector level:
I
The sector lock/unlock command sequence dis-
ables or re-enables both program and erase opera-
tions in any sector.
I
When WP# is at V
IL
,
the two outermost sectors are
locked.
I
When V
PP
is at V
IL
, all sectors are locked.
The following hardware data protection measures pre-
vent accidental erasure or programming, which might
otherwise be caused by spurious system level signals
during V
CC
power-up and power-down transitions, or
from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to reading array data. Subse-
quent writes are ignored until V
CC
is greater than
V
LKO
. The system must provide the proper signals to
the control inputs to prevent unintentional writes when
V
CC
is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
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