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參數(shù)資料
| 型號： | AM29BDS320GBD4VMI |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 32 Megabit (2 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 2M X 16 FLASH 1.8V PROM, 70 ns, PBGA64 |
| 封裝： | 8 X 9 MM, 0.80 MM PITCH, FBGA-64 |
| 文件頁數(shù)： | 18/74頁 |
| 文件大?。?/td> | 701K |
| 代理商： | AM29BDS320GBD4VMI |
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16
Am29BDS320G
27243B1 October 1, 2003
P r e l i m i n a r y
cycle program command sequence as required by the Unlock Bypass mode. Re-
moving V
ID
from the ACC input returns the device to normal operation. Note that
sectors must be unlocked prior to raising ACC to V
ID
.
Note that the ACC pin must
not be at V
ID
for operations other than accelerated programming, or device dam-
age may result. In addition, the ACC pin must not be left floating or unconnected;
inconsistent behavior of the device may result
.
When at V
IL
, ACC locks all sectors. ACC should be at V
IH
for all other conditions.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the au-
toselect mode. The system can then read autoselect codes from the internal
register (which is separate from the memory array) on DQ15–DQ0. Autoselect
mode may only be entered and used when in the asynchronous read mode. Refer
to the
“Autoselect Command Sequence” section on page 30
section for more
information.
Standby Mode
When the system is not reading or writing to the device, it can place the device
in the standby mode. In this mode, current consumption is greatly reduced, and
the outputs are placed in the high impedance state, independent of the OE#
input.
The device enters the CMOS standby mode when the CE# and RESET# inputs are
both held at V
CC
± 0.2 V. The device requires standard access time (t
CE
) for read
access, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
I
CC3
in the DC Characteristics table represents the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. While in
asynchronous mode, the device automatically enables this mode when addresses
remain stable for t
ACC
+ 60 ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output data is
latched and always available to the system. While in synchronous mode, the de-
vice automatically enables this mode when either the first active CLK edge occurs
after t
ACC
or the CLK runs slower than 5MHz. Note that a new burst operation is
required to provide new data.
I
CC4
in the
“DC Characteristics” section on page 44
represents the automatic
sleep mode current specification.
RESET#: Hardware Reset Input
The RESET# input provides a hardware method of resetting the device to reading
array data. When RESET# is driven low for at least a period of t
RP
, the device im-
mediately terminates any operation in progress, tristates all outputs, resets the
configuration register, and ignores all read/write commands for the duration of
the RESET# pulse. The device also resets the internal state machine to reading
array data. The operation that was interrupted should be reinitiated once the de-
vice is ready to accept another command sequence, to ensure data integrity.
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